| 1. |
- Candaele, Bernard, et al.
(författare)
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Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach
- 2010
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Ingår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 518-523
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Konferensbidrag (refereegranskat)abstract
- The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
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| 2. |
- Candaele, Bernard, et al.
(författare)
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The MOSART Mapping Optimization for multi-core Architectures
- 2011
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Ingår i: VLSI 2010 Annual Symposium. - Dordrecht : Springer Publishing Company. ; , s. 181-195
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Konferensbidrag (refereegranskat)abstract
- MOSART project addresses two main challenges of prevailing architectures: (i) Theglobal interconnect and memory bottleneck due to a single, globally shared memorywith high access times and power consumption; (ii) The difficulties in programmingheterogeneous, multi-core platforms MOSART aims to overcome these through amulti-core architecture with distributed memory organization, a Network-on-Chip(NoC) communication backbone and configurable processing cores that are scaled,optimized and customized together to achieve diverse energy, performance, cost andsize requirements of different classes of applications. MOSART achieves this by:(i) Providing platform support for management of abstract data structures includingmiddleware services and a run-time data manager for NoC based communicationinfrastructure; (ii) Developing tool support for parallelizing and mapping applicationson the multi-core target platform and customizing the processing cores for theapplication.
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| 3. |
- Soudris, Dimitrios, et al.
(författare)
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AEGLE : A Big Bio-Data Analytics Framework for Integrated Health-Care Services
- 2015
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Ingår i: Proceedings International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS XV). - 9781467373111 ; , s. 246-253
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Konferensbidrag (refereegranskat)abstract
- AEGLE project(1) targets to build an innovative ICT solution addressing the whole data value chain for health based on: cloud computing enabling dynamic resource allocation, HPC infrastructures for computational acceleration and advanced visualization techniques. In this paper, we provide an analysis of the addressed Big Data health scenarios and we describe the key enabling technologies, as well as data privacy and regulatory issues to be integrated into AEGLE's ecosystem, enabling advanced health-care analytic services, while also promoting related research activities.
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| 4. |
- Stathis, Dimitrios, 1989-
(författare)
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Synchoros VLSI Design Style
- 2022
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Computers have become essential to everyday life as much as electricity, communications and transport. That is evident from the amount of electricity we spend to power our computing systems. According to some reports it is estimated to be ≈ 7% of the total consumption worldwide. This trend is very worrisome, and the development of computing systems with lower power consumption is essential. This is even more important for battery-powered computers deployed in the field. The industry and the scientific community have realised that general-purpose computing platforms cannot offer that level of computational efficiency and that customisation is the solution to this problem. Application-Specific Integrated Circuits (ASICs) provide the highest efficiency in the mainstream implementation styles. ASICs have been shown to provide 100 to 1000× better computational efficiency than general-purpose computing platforms. However, the design cost of ASICs restricts it to products that have a large volume or large profit. In essence, to achieve ASIC-like computational efficiency, the design efficiency becomes the bottleneck. SynchorosVLSI design has been proposed to non-incrementally lower the design cost of custom ASIC-like solutions. The synchoros VLSI design is a novel concept that can reduce the design cost of ASICs and their manufacturing. Insynchoros design, the space is discretised, and the final design emerges by the abutment of synchoros micro-architecture level design objects called SiLago(Silicon Lego) blocks. The SiLago framework has the potential to reduce the design cost of ASICs and their manufacturing. This thesis makes three research areas of contributions toward synchoros VLSI design. The first area concerns composition by abutment. In this contribution, a design has been proposed to show how a clock tree can be created by abutting fragments inside the SiLago blocks. Additionally, the clock tree created by abutment was validated by the EDA tools and its cost metrics compared to the functionally equivalent clock tree created by the conventional EDA flows. The second area is to enhance the micro-architectural framework. These contributions include SiLago blocks tailored for neural network computation and architectural enhancements to improve the efficiency of executing streaming applications in the SiLago framework. Furthermore, a novel genome recognition application based on a self-organising map (SOM) was also mapped to the SiLago framework. The third area of contribution is implementing a model of cortex as a tiled ASIC design using custom 3D DRAM vaults for synaptic storage. This work is preparatory work to identify the SiLago blocks needed to support the implementation of spiking neuromorphic structures and in general applications of ordinary differential equations.
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| 5. |
- Anagnostopoulos, Iraklis, et al.
(författare)
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Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
- 2011
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Ingår i: IEEE Embedded Systems Letters. - 1943-0663. ; 3:2, s. 66-69
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Tidskriftsartikel (refereegranskat)abstract
- Multiprocessor system-on-chip (MPSoCs) have attracted significant attention since they are recognized as a scalable paradigm to interconnect and organize a high number of cores. Current multicore embedded systems exhibit increased levels of dynamicbehavior, leading to unexpected memory footprint variations unknown at design time.Dynamic memory management (DMM) is a promising solution for such types of dynamicsystems. Although some efficient dynamic memory managers have been proposed for conventional bus-based MPSoC platforms, there are no DMM solutions regarding the constraints and the opportunities delivered by the physical distribution of multiple memorynodes of the platform. In this work, we address the problem of providing customizedmicrocoded DMM on MPSoC platforms with distributed memory organization. Customization is enabled at application-and platform-level. Results show that customizedmicrocoded DMM can serve approximately 7× more allocation requests compared to puredistributed memory platforms and perform 25% faster than the corresponding high-level implementation in C language.
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| 6. |
- Aviles, Marcos, et al.
(författare)
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A co-design methodology for implementing computer vision algorithms for rover navigation onto reconfigurable hardware
- 2011
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Ingår i: Proceedings of the FPL2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures. ; , s. 9-10
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Vision-based robotics applications have been widely studied in the last years. However, up to now solutions that have been proposed were affecting mostly software level. The SPARTAN project focuses in the tight and optimal implementation of computer vision algorithms targeting to rover navigation. For evaluation purposes, these algorithms will be implemented with a co-design methodology onto a Virtex-6 FPGA device.
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| 7. |
- Panagiotou, Sotirios, et al.
(författare)
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Portable exploitation of parallel and heterogeneous HPC architectures in neural simulation using SkePU
- 2020
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Ingår i: PROCEEDINGS OF THE 23RD INTERNATIONAL WORKSHOP ON SOFTWARE AND COMPILERS FOR EMBEDDED SYSTEMS (SCOPES 2020). - New York, NY, USA : ASSOC COMPUTING MACHINERY. - 9781450371315 ; , s. 74-77
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Konferensbidrag (refereegranskat)abstract
- The complexity of modern HPC systems requires the use of new tools that support advanced programming models and offer portability and programmability of parallel and heterogeneous architectures. In this work we evaluate the use of SkePU framework in an HPC application from the neural computing domain. We demonstrate the successful deployment of the application based on SkePU using multiple back-ends (OpenMP, OpenCL and MPI) and present lessons-learned towards future extensions of the SkePU framework.
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| 8. |
- Papadopoulos, Lazaros, et al.
(författare)
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EXA2PRO : A Framework for High Development Productivity on Heterogeneous Computing Systems
- 2022
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Ingår i: IEEE Transactions on Parallel and Distributed Systems. - : IEEE Computer Society. - 1045-9219 .- 1558-2183. ; 33:4, s. 792-804
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Tidskriftsartikel (refereegranskat)abstract
- Programming upcoming exascale computing systems is expected to be a major challenge. New programming models are required to improve programmability, by hiding the complexity of these systems from application developers. The EXA2PRO programming framework aims at improving developers productivity for applications that target heterogeneous computing systems. It is based on advanced programming models and abstractions that encapsulate low-level platform-specific optimizations and it is supported by a runtime that handles application deployment on heterogeneous nodes. It supports a wide variety of platforms and accelerators (CPU, GPU, FPGA-based Data-Flow Engines), allowing developers to efficiently exploit heterogeneous computing systems, thus enabling more HPC applications to reach exascale computing. The EXA2PRO framework was evaluated using four HPC applications from different domains. By applying the EXA2PRO framework, the applications were automatically deployed and evaluated on a variety of computing architectures, enabling developers to obtain performance results on accelerators, test scalability on MPI clusters and productively investigate the degree by which each application can efficiently use different types of hardware resources.
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| 9. |
- Smaragdos, G., et al.
(författare)
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BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations
- 2017
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Ingår i: Journal of Neural Engineering. - : IOP Publishing. - 1741-2560 .- 1741-2552. ; 14:6
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Tidskriftsartikel (refereegranskat)abstract
- Objective: The advent of High-Performance Computing (HPC) in recent years has led to its increasing use in brain study through computational models. The scale and complexity of such models are constantly increasing, leading to challenging computational requirements. Even though modern HPC platforms can often deal with such challenges, the vast diversity of the modeling field does not permit for a homogeneous acceleration platform to effectively address the complete array of modeling requirements. Approach: In this paper we propose and build BrainFrame, a heterogeneous acceleration platform that incorporates three distinct acceleration technologies, an Intel Xeon-Phi CPU, a NVidia GP-GPU and a Maxeler Dataflow Engine. The PyNN software framework is also integrated into the platform. As a challenging proof of concept, we analyze the performance of BrainFrame on different experiment instances of a state-of-the-art neuron model, representing the Inferior-Olivary Nucleus using a biophysically-meaningful, extended Hodgkin-Huxley representation. The model instances take into account not only the neuronal-network dimensions but also different network-connectivity densities, which can drastically affect the workload's performance characteristics. Main results: The combined use of different HPC fabrics demonstrated that BrainFrame is better able to cope with the modeling diversity encountered in realistic experiments. Our performance analysis shows clearly that the model directly affects performance and all three technologies are required to cope with all the model use cases. Significance: The BrainFrame framework is designed to transparently configure and select the appropriate back-end accelerator technology for use per simulation run. The PyNN integration provides a familiar bridge to the vast number of models already available. Additionally, it gives a clear roadmap for extending the platform support beyond the proof of concept, with improved usability and directly useful features to the computational-neuroscience community, paving the way for wider adoption.
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| 10. |
- Soudris, Dimitrios, et al.
(författare)
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EXA2PRO programming environment: Architecture and Applications
- 2018
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Ingår i: 2018 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION (SAMOS XVIII). - New York, NY, USA : ASSOC COMPUTING MACHINERY. - 9781450364942 ; , s. 202-209
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Konferensbidrag (refereegranskat)abstract
- The EXA2PRO programming environment will integrate a set of tools and methodologies that will allow to systematically address many exascale computing challenges, including performance, performance portability, programmability, abstraction and reusability, fault tolerance and technical debt. The EXA2PRO tool-chain will enable the efficient deployment of applications in exascale computing systems, by integrating high-level software abstractions that offer performance portability and efficient exploitation of exascale systems heterogeneity, tools for efficient memory management, optimizations based on trade-offs between various metrics and fault-tolerance support. Hence, by addressing various aspects of productivity challenges, EXA2PRO is expected to have significant impact in the transition to exascale computing, as well as impact from the perspective of applications. The evaluation will be based on 4 applications from 4 different domains that will be deployed in JUELICH supercomputing center. The EXA2PRO will generate exploitable results in the form of a tool-chain that support diverse exascale heterogeneous supercomputing centers and concrete improvements in various exascale computing challenges.
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