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- Agirre, J. A., et al.
(författare)
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The VALU3S ECSEL project : Verification and validation of automated systems safety and security
- 2021
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Ingår i: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 87, s. 104349-
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Tidskriftsartikel (refereegranskat)abstract
- Manufacturers of automated systems and their components have been allocating an enormous amount of time and effort in R&D activities, which led to the availability of prototypes demonstrating new capabilities as well as the introduction of such systems to the market within different domains. Manufacturers need to make sure that the systems function in the intended way and according to specifications. This is not a trivial task as system complexity rises dramatically the more integrated and interconnected these systems become with the addition of automated functionality and features to them. This effort translates into an overhead on the V&V (verification and validation) process making it time-consuming and costly. In this paper, we present VALU3S, an ECSEL JU (joint undertaking) project that aims to evaluate the state-of-the-art V&V methods and tools, and design a multi-domain framework to create a clear structure around the components and elements needed to conduct the V&V process. The main expected benefit of the framework is to reduce time and cost needed to verify and validate automated systems with respect to safety, cyber-security, and privacy requirements. This is done through identification and classification of evaluation methods, tools, environments and concepts for V&V of automated systems with respect to the mentioned requirements. VALU3S will provide guidelines to the V&V community including engineers and researchers on how the V&V of automated systems could be improved considering the cost, time and effort of conducting V&V processes. To this end, VALU3S brings together a consortium with partners from 10 different countries, amounting to a mix of 25 industrial partners, 6 leading research institutes, and 10 universities to reach the project goal.
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| 3. |
- Batista, Gracieth Cavalcanti, et al.
(författare)
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Machine learning algorithm partially reconfigured on FPGA for an image edge detection system
- 2024
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Ingår i: Journal of Electronic Science and Technology. - : Elsevier BV. - 1674-862X. ; 22:2
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Tidskriftsartikel (refereegranskat)abstract
- Unmanned aerial vehicles (UAVs) have been widely used in military, medical, wireless communications, aerial surveillance, etc. One key topic involving UAVs is pose estimation in autonomous navigation. A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system (GNSS) signal. However, some factors can interfere with the GNSS signal, such as ionospheric scintillation, jamming, or spoofing. One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images. But a high effort is required for image edge extraction. In this paper, a support vector regression (SVR) model is proposed to reduce this computational load and processing time. The dynamic partial reconfiguration (DPR) of part of the SVR datapath is implementated to accelerate the process, reduce the area, and analyze its granularity by increasing the grain size of the reconfigurable region. Results show that the implementation in hardware is 68 times faster than that in software. This architecure with DPR also facilitates the low power consumption of 4 mW, leading to a reduction of 57% than that without DPR. This is also the lowest power consumption in current machine learning hardware implementations. Besides, the circuitry area is 41 times smaller. SVR with Gaussian kernel shows a success rate of 99.18% and minimum square error of 0.0146 for testing with the planning trajectory. This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application, thus contributing to lower power consumption, smaller hardware area, and shorter execution time.
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- Collin, Mikael, et al.
(författare)
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A performance and energy exploration of dictionary code compression architectures
- 2011
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Ingår i: 2011 International Green Computing Conference and Workshops (IGCC). - : IEEE conference proceedings. - 9781457712227 ; , s. 1-8
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Konferensbidrag (refereegranskat)abstract
- We have made a performance and energy exploration of a previously proposed dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. Our simulated design shows a dramatically reduced instruction memory access frequency leading to a performance improvement for small instruction cache sizes and to significantly reduced energy consumption in the instruction fetch path. We have evaluated the performance and energy implications of three architectural parameters: branch prediction accuracy, instruction cache size and organization. To asses the complexity of the design we have implemented the critical stages in VHDL.
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- Deb, Abhijit Kumar, et al.
(författare)
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Hardware software codesign of DSP system using grammar based approach
- 2001
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Ingår i: VLSI Design, 2001. Fourteenth International Conference on. ; , s. 42-47
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Konferensbidrag (refereegranskat)abstract
- Embedded cores are gaining widespread use to deal with the complex DSP systems where flexibility is of utmost importance. The design of such a system offers several problems, which are not addressed by the existing methodology. The authors previously presented an integrated grammar based DSP design methodology that separates architectural and functional specification, can create a virtual prototype and has a smooth link to the implementation phase. In this paper we present the extension of the work to handle embedded cores. Here we the capture the host peripheral interface (HPI) of TMS320C6x core at higher level of abstraction and provide a single simulation environment, which facilitates faster analysis of hardware software components. Our results reveal that the proposed methodology offers simulation time speed-up of 5 times and design time speed-up of 8 times, while keeping the architectural specification separated from functionality
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