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- Andersson, Daniel, 1977, et al.
(author)
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On Skin Effect in On-Chip Interconnects
- 2004
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In: Intl Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). - Berlin, Heidelberg : Springer Berlin Heidelberg. ; , s. 463-470
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Conference paper (peer-reviewed)abstract
- We investigate the influence of skin effect on the propagation delays of on-chip interconnects. For long wires, designed in the LC regime, on the top metal layer in a contemporary process, we find that the skin effect causes an extra delay by 10%. The impact of the skin effect on delay is furthermore rapidly increasing with increased interconnect width.
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- Do, Minh Quang, 1969, et al.
(author)
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Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
- 2004
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In: Lecture Notes in Computer Science (LNCS) , Springer Verlag. - Berlin, Heidelberg : Springer Berlin Heidelberg. ; 3254:1, s. 869-878
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Conference paper (peer-reviewed)abstract
- In this paper, we propose the White-box Table-based Total Power Consumption (WTTPC) estimation approach that offers both rapid and accurate architecture-level power estimation models for some processor components with regular structures, such as SRAM arrays, based on WTTPC-tables ofpower values. A comparison of power estimates obtained from the proposed approach against circuit-level HSPICE power values for a 64-b conventional 6T-SRAM memory array implemented in a commercial 0.13-um CMOS technology process shows a 98% accuracy of the WTTPC approach.
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