| 1. |
- Henriksson, Tomas, et al.
(author)
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Network Calculus Applied to Verification of Memory Access Performance in SoCs
- 2007
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In: Proceedings of the 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007. - 9781424416547 ; , s. 21-26
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Conference paper (peer-reviewed)abstract
- SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of a SoC under design hard to predict. Network calculus defines the concept of flow and has been successfully used to analyse the performance of communication networks. We propose to apply network calculus to the verification of memory access latencies. Two novel network elements, packet stretcher and packet compressor, are used to model the SoC interconnect and DRAM controller. We further extend the flow concept with a degree and make use of the peak characteristics of a flow to tighten the bounds in the analysis. We present a video playback case study and show that the proposed application of network calculus allows us to statically verify that all requirements on memory access latency are fulfilled.
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| 2. |
- Lu, Zhonghai, et al.
(author)
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Flow Regulation for On-Chip Communication
- 2009
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In: DATE. - 9781424437818 ; , s. 578-581
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Conference paper (peer-reviewed)abstract
- We propose (sigma, rho)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where sigma bounds the traffic burstiness and rho the traffic rate. This regulation changes the burstiness and timing of traffic flows, and can be used to decrease delay and reduce buffer requirements in the SoC infrastructure. In this paper, we define and analyze the regulation spectrum, which bounds the upper and lower limits of regulation. Experiments on a Network-on-Chip (NoC) with guaranteed service demonstrate the benefits of regulation We conclude that flow regulation may exert significant positive impact on communication performance and buffer requirements.
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| 3. |
- Wolf, Pieter van der, et al.
(author)
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Definition of Device Level Interface with QoS : Draft Specification
- 2007
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Reports (other academic/artistic)abstract
- The extensions to standard IP communication interfaces proposed in SPRINT WP3document D3.1 are defined. Flow identification signals are added to the DLI signal level interface so transactionscan indicate the services they require. These services are specified as Contracts thatdefine the flow characteristics required for correct operation. These characteristics arethe main input to an analysis method to validate that a SoC design achieves its performance targets. DLI-Guard units are defined that enforce Contracts by regulating an IP module’s identified flows. Monitoring of flow characteristics, such as latency, is also optionally provided. A configuration API for DLI-Guards is outlined together with example code toillustrate its use. This specification is successfully applied to AMBA AXI, the prime example DLI
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