Modelling accesses to stationary data in a shared memory multiprocessor

• Cache misses due to coherence and directory maintenance is a major reason for poor performance in shared memory multiprocessors. We show that the relationship between a particular access pattern and cache miss ratios for a class of directory-based, write-invalidate cache coherence protocols can be characterised in a small set of parameters. In order to do this, a reference generator has been designed that, based on parameters automatically extracted from a program, can artificially generate a reference stream that results in the same cold, coherence and directory replacement miss ratios as an execution of the program.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)

Publikations- och innehållstyp

ref (ämneskategori)

kon (ämneskategori)