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A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers
- 2002
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200 .- 1558-173X. ; 37:9, s. 1162-1168
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Tidskriftsartikel (refereegranskat)abstract
- A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in RF Si-bipolar process with an f(T) of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP3 (+15.5-dBm OIP3) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA dc current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with - 10 to -41-dB S-11 is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 x 0.9 mm(2). The circuit is suitable for area-efficient multiband multistandard low-IF receivers.
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| 2. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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A sub-130-nm conditional keeper technique
- 2002
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:5, s. 633-638
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Tidskriftsartikel (refereegranskat)abstract
- Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction
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| 4. |
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| 5. |
- Alzaher, H. A., et al.
(författare)
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A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers
- 2002
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:1, s. 27-37
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Tidskriftsartikel (refereegranskat)abstract
- A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.
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| 6. |
- Andersson, Mattias, et al.
(författare)
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A Filtering Delta Sigma ADC for LTE and Beyond
- 2014
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 49:7, s. 1535-1547
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Tidskriftsartikel (refereegranskat)abstract
- Abstract in UndeterminedThis paper presents a filtering ADC for the LTE communication standard, where a second-order Delta-Sigma modulator (DSM) is incorporated into the third-order Chebychev channel-select filter (CSF) of the radio receiver. The CSF introduces an additional third-order suppression of both thermal and quantization DSM noise, while the CSF transfer function is maintained. A design method for the filtering ADC accounting for unavoidable DSM-DAC delays is developed and experimentally demonstrated. The 65 nm CMOS prototype is clocked at 576/288 MHz with an 18.5/9.0 MHz LTE bandwidth, has an in-band gain of 26 dB, an SNDR of 56.4/58.1 dB, an input-referred noise of 5 nV/root Hz, and an out-of-band (half-duplex) IIP3 of 20/12 dBV(rms), with a power consumption of 7.9/5.4 mW and an overall state-of-the art performance.
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| 7. |
- Andersson, Martin, et al.
(författare)
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Design and measurement of a CT delta-sigma ADC with switched-capacitor switched-resistor feedback
- 2009
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 44:2, s. 473-483
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Tidskriftsartikel (refereegranskat)abstract
- The performance of traditional continuous-time (CT) delta-sigma analog-to-digital converters (ADCs) is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback digital-to-analog converters (DACs). To mitigate that effect, we propose a modified switched-capacitor (SC) feedback DAC technique, with a variable switched series resistor (SR). The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. A theoretical investigation is carried out which provides new insight into the synthesis of switched-capacitor with switched series resistor (SCSR) DACs with a specified reduction of the pulse-width jitter sensitivity and minimal power consumption and complexity. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz, second order, low-pass, 1-bit, CT delta-sigma modulator with SCSR feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process. An SNR of 66.4 dB and an SNDR of 62.4 dB were measured in a 1.92 MHz bandwidth. The sensitivity to wideband clock phase noise was reduced by 30 dB compared to a traditional switched-current (SI) return-to-zero (RZ) DAC.
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| 8. |
- Andreani, Pietro, et al.
(författare)
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A 2.2 GHz CMOS VCO with inductive degeneration noise suppression
- 2001
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Ingår i: Proceedings of the IEEE 2001 Custom Integrated Circuits Conference. - 0018-9200. ; , s. 197-200
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Konferensbidrag (refereegranskat)abstract
- A 1.4 V, 9 mA monolithic LC-tank voltage-controlled oscillator (VCO) fabricated in a standard 0.35 μm CMOS process is presented. The VCO is tunable between 2.0 GHz and 2.37 GHz, and displays a phase noise between -140 dBc/Hz and -138 dBc/Hz at a 3 MHz offset frequency across the whole tuning range. This low phase noise is achieved through the use of an on-chip LC filter and an off-chip low frequency inductor, which totally remove the noise of the tail current source. The phase noise improvement due to the off-chip inductor is between 2 dB and 6 dB, increasing with higher oscillation frequencies
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| 9. |
- Andreani, Pietro, et al.
(författare)
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A Study of Phase Noise in Colpitts and LC-tank CMOS Oscillators
- 2005
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200 .- 1558-173X. ; 40:5, s. 1107-1118
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f2 phase-noiseregion are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise flgure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypesof both Colpitts and LC-tank oscillators have been implemented in a 0.35-μm CMOS process. The best performance of the LC-tank oscillatorsshows a phase noise of - 142 dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of ∼189 dBc/Hz. For the same oscillation frequency, the FoM displayed by the differential Colpitts oscillators is ∼5 dB lower.
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| 10. |
- Andreani, Pietro, et al.
(författare)
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A TX VCO for WCDMA/EDGE in 90 nm RF CMOS
- 2011
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 46:7, s. 1618-1626
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Tidskriftsartikel (refereegranskat)abstract
- A VCO is implemented in an RF 90 nm CMOS process and covers the frequency range 2.55-4.08 GHz. Drawing 19 mA from 1.2 V, the phase noise at 20 MHz frequency offset from a 3.7 GHz carrier is -156 dBc/Hz, meeting the phase noise requirement for GSM/EDGE and SAW-less WCDMA transmitter after frequency division by 2 or by 4. A second version of the VCO covers an additional 4.90-5.75 GHz range, at the expense of a higher phase noise in the added band. In this way, all currently operational WCDMA/EDGE bands can be synthesized by a single VCO working at the double or quadruple of the desired band. A technique for shortening the transient response of the VCO during frequency tuning is also presented.
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