| 1. |
- Arshad, Sana, et al.
(författare)
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50-830 MHz noise and distortion canceling CMOS low noise amplifier
- 2018
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Ingår i: Integration. - : Elsevier. - 0167-9260 .- 1872-7522. ; 60, s. 63-73
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a modified resistive shunt feedback topology is proposed that performs noise cancelation and serves as an opposite polarity non-linearity generator to cancel the distortion produced by the main stage. The proposed topology has a bandwidth similar to a resistive shunt feedback LNA, but with a superior noise figure (NF) and linearity. The proposed wideband LNA is fabricated in 130 nm CMOS technology and occupies an area of 0.5 mm(2). Measured results depict 3-dB bandwidth from 50 to 830 MHz. The measured gain and NF at 420 MHz are 17 dB and 2.2 dB, respectively. The high value of the 1/f noise is one of the key problems in low frequency CMOS designs. The proposed topology also addresses this challenge and a low NF is attained at low frequencies. Measured 811 and S22 are better than -8.9 dB and -8.5 dB, respectively within the 0.05-1 GHz band. The 1-dB compression point is -11.5 dBm at 700 MHz, while the IIP3 is -6.3 dBm. The forward core consumes 14 mW from a 1.8 V supply. This LNA is suitable for VHF and UHF SDR communication receivers.
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| 2. |
- Asif, Shahzad, et al.
(författare)
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Performance analysis of radix-4 adders
- 2012
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Ingår i: Integration. - : Elsevier. - 0167-9260 .- 1872-7522. ; 45:2, s. 111-120
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Tidskriftsartikel (refereegranskat)abstract
- We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carry-based adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4 circuit is 24% faster than a 2-bit radix-2 ripple carry adder with slightly larger transistor count, whereas the power consumption is almost the same. A second scheme for radix-2 and radix-4 adders that have a reduced number of transistors in the carry path is also investigated. Simulation results also confirm that the radix-4 adder gives better performance as compared to a standard 2-bit CLA. 32-Bit ripple carry, 2-stage carry select, variable size carry select, and carry skip adders are implemented with the different full adders as building blocks. There are POP savings, with one exception, for the 32-bit adders in the range 8-18% and EDP savings in the range 21-53% using radix-4 as compared to radix-2.
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| 3. |
- Attarzadeh-Niaki, S. -H, et al.
(författare)
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An automated parallel simulation flow for cyber-physical system design
- 2021
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Ingår i: Integration. - : Elsevier BV. - 0167-9260 .- 1872-7522. ; 77, s. 48-58
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Tidskriftsartikel (refereegranskat)abstract
- Parallel and distributed simulation (PDS) is often employed to tackle the computational intensity of system-level simulation of real-world complex embedded and cyber-physical systems (CPSs). However, CPS models comprise heterogeneous components with diverge semantics for which incompatible PDS approaches are developed. We propose an automated PDS flow based on a formal modeling framework—with necessary extensions—targeting heterogeneous embedded and CPS design. The proposed flow characterizes the sequential executable specification of a heterogeneous model and generates a PDS cluster. State-of-the-art graph partitioning methods are adopted and a new extensible constraint-base formulation of the model partitioning problem is developed. The applicability, effectiveness, and scalability of the proposed flow is demonstrated using case studies.
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| 4. |
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| 5. |
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| 6. |
- Harikumar, Prakash, et al.
(författare)
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A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
- 2015
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Ingår i: Integration. - : Elsevier. - 0167-9260 .- 1872-7522. ; 50, s. 28-38
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.
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| 7. |
- Hassanli, Kourosh, et al.
(författare)
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A low-power wide tuning-range CMOS current-controlled oscillator
- 2016
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Ingår i: Integration. - : ELSEVIER SCIENCE BV. - 0167-9260 .- 1872-7522. ; 55, s. 57-66
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 mu A, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 my. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8 x 11.5 mu m(2). (C) 2016 Elsevier B.V. All rights reserved.
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| 8. |
- Jalili, Armin, et al.
(författare)
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A nonlinearity error calibration technique for pipelined ADCs
- 2011
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Ingår i: Integration. - Amsterdam, The Netherlands : Elsevier. - 0167-9260 .- 1872-7522. ; 44:3, s. 229-241
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.
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| 9. |
- Jiang, Shuyan, et al.
(författare)
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Testing aware dynamic mapping for path-centric network-on-chip test
- 2019
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Ingår i: Integration. - : Elsevier. - 0167-9260 .- 1872-7522. ; 67, s. 134-143
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Tidskriftsartikel (refereegranskat)abstract
- With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the primary goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle paths are identified, and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from the time when the application leaves the platform to the time when a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping, which leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF(Fiexitrst Free), NN(Nearest Neighbor), CoNA(Contiguous Neighborhood Allocation), and WeNA(Weighted-based Neighborhood Allocation).
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| 10. |
- Ma, Ning, et al.
(författare)
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Design and Implementation of Multi-mode Routers for Large-scale Inter-core Networks
- 2016
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Ingår i: Integration. - : Elsevier. - 0167-9260 .- 1872-7522. ; 53, s. 1-13
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)abstract
- Constructing on-chip or inter-silicon (inter-die/inter-chip) networks to connect multiple processors extends the system capability and scalability. It is a key issue to implement a flexible router that can fit into various application scenarios. This paper proposes a multi-mode adaptable router that can support both circuit and wormhole switching with supplying flexible working strategies for specific traffic patterns in diverse applications. The limitation of mono-mode switched routers is shown at first, followed by algorithm exploration in the proposed router for choosing the proper working strategy in a specific network. We then present the performance improvement when applying the mixed circuit/wormhole switching mode to different applications, and analyze the image decoding as a case study. The multi-mode router has been implemented with different configurations in a 65 nm CMOS technology. The one with 8-bit flit width is demonstrated together with a multi-core processor to show the feasibility. Working at 350 MHz, the average power consumption of the whole system is 22 mW.
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