| 1. |
- Chub, Andrii, et al.
(författare)
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CCM and DCM Analysis of Quasi-Z-Source Derived Push-Pull DC/DC Converter
- 2014
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Ingår i: Informacije midem. - 0352-9045. ; 44:3, s. 224-234
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a steady state analysis of the operation modes of the quasi-Z-source (qZS) derived push-pull DC/DC converter topology. It was derived by the combination of the qZS network and coupled inductors. The output stage of the converter consists of a diode bridge rectifier and an LC-filter. This topology provides a wide regulation range of the input voltage and galvanic isolation. These features fit the requirements for the integration systems of renewable energy sources, such as PV panels, variable speed wind turbines, and fuel cells. A converter can operate in continuous (CCM) and discontinuous conduction mode (DCM). Switching period is divided into four and six intervals for CCM and DCM, respectively. Equivalent circuits and analytical expressions for each interval are presented. The DC gain factor for each mode is derived. To simplify our analysis, coupled inductors were substituted with a model that consists of an ideal transformer and magnetizing inductance. Leakage inductances are neglected because the coupling coefficient in this topology should be close to unity. In DCM the converter operation depends on the active duty cycle and the duty cycle of the zero current condition. Two solutions are possible for the DC gain factor in DCM. It is theoretically impossible to achieve the unity DC gain factor in DCM if the turns ratio of coupled inductors is equal to or more than one. The proposed topology was simulated with PSIM software in two operating points. Experimental verification proves our theoretical and simulation results.
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| 2. |
- Kovacic, M., et al.
(författare)
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Modelling Supported Design of Light Management Structures in Ultra-Thin Cigs Photovoltaic Devices
- 2019
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Ingår i: Informacije midem. - : Drustvo MIDEM. - 0352-9045. ; 49:3, s. 183-190
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Tidskriftsartikel (refereegranskat)abstract
- Chalcopyrite solar cells exhibit one of the highest conversion efficiencies among thin-film solar cell technologies (> 23.3%), however a considerably thick absorber >= 1.8 mu m is required for an efficient absorption of the long-wavelength light and collection of charge carriers. In order to minimize the material consumption and to accelerate the fabrication process, further thinning down of the absorber layer is important. Using a thin absorber layer results in a highly reduced photocurrent density and to compensate for it an effective light management needs to be introduced. Experimentally supported, advanced optical simulations in a PV module configuration, i.e. solar cell structure including the encapsulation and front glass are employed to design solutions to increase the short current density of devices with ultra-thin (500 nm) absorbers. In particular (i) highly reflective metal back reflector (BR), (ii) internal nano-textures and (iii) external textures by applying a light management (LM) foil are investigated by simulations. Experimental verification of simulation results is presented for the external texture case. In the scope of this contribution we show that any individual aforementioned approach is not sufficient to compensate for the short circuit current drop of the thin CIGS, but only a combination of highly reflective back contact and introduction of textures (internal or external) is able to compensate and also to exceed (by more than 5 % for internal texture) photocurrent density of a thick (1800 nm) CIGS absorber.
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| 3. |
- Peng, Zebo, et al.
(författare)
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Challenges and solutions for thermal-aware SOC testing
- 2007
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Ingår i: Informacije midem. - 0352-9045. ; 37:4, s. 220-227
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Tidskriftsartikel (refereegranskat)abstract
- High temperature has negative impact on the performance, reliability and lifespan of a system on chip. During testing, the chip can be overheated due to a substantial increase of switching activities and concurrent tests in order to reduce test application time. This paper discusses several issues related to the thermal problem during SoC testing. It will then present a thermal-aware SoC test scheduling technique to generate the shortest test schedule such that the temperature constraints of individual cores and the constraint on the test-bus bandwidth are satisfied. In order to avoid overheating during the test, we partition test sets into shorter test sub-sequences and add cooling periods in between. Further more, we interleave the test sub-sequences from different test sets in such a manner that the test-bus bandwidth reserved for one core is utilized during its cooling period for the test transportation and application of the other cores. We have developed a heuristic to minimize the test application time by exploring alternative test partitioning and interleaving schemes with variable length of test sub-sequences and cooling periods. Experimental results have shown the efficiency of the proposed heuristic.
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