| 1. |
- He, Zhiyuan, 1976-, et al.
(författare)
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Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
- 2005
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Ingår i: 8th Euromicro Conference on Digital System Design DSD2005,2005. - Porto, Portugal : IEEE Computer Society Press. - 0769524338 ; , s. 83-
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Konferensbidrag (refereegranskat)abstract
- This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detected. We employ the defect probabilities of individual cores to guide the scheduling, such that the expected total test time is minimized and the peak power constraint is satisfied. Based on a hybrid BIST architecture where a combination of deterministic and pseudorandom test sequences is used, the power-constrained test scheduling problem can be formulated as an extension of the two-dimensional rectangular packing problem and a heuristic has been proposed to calculate the near optimal order of different test sequences. The method is also generalized for both test-per-clock and test-per-scan approaches. Experimental results have shown that the proposed heuristic is efficient to find a near optimal test schedule with a low computation overhead.
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| 2. |
- Karlsson, Daniel, 1975-, et al.
(författare)
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Validation of Embedded Systems using Formal Method aided Verification
- 2005
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Ingår i: 8th Euromicro Conference on Digital System Design DSD2005,2005. - Porto, Portugal : IEEE Computer Society Press. - 0769524338 ; , s. 196-
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Konferensbidrag (refereegranskat)abstract
- Informal validation techniques, such as simulation, suffer from the fact that they only examine a small fraction of the state space. Formal techniques, on the other hand, suffer from state space explosion and are not practical to use for huge, complex systems. This paper proposes a validation approach, based on simulation, which addresses some of the above problems. Formal methods, in particular model checking, are used to aid the simulation process in certain situations in order to boost coverage. The invocation frequency of the model checker is dynamically controlled by estimating certain parameters, based on statistics collected previously during the same validation session, in order to minimise verification time and at the same time achieve reasonable coverage. The approach has been demonstrated feasible by numerous experimental results.
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| 3. |
- Larsson, Anders, 1977-, et al.
(författare)
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Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
- 2005
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Ingår i: 8th Euromicro Conference on Digital System Design DSD2005,2005. - Porto, Portugal : IEEE Computer Society Press. - 0769524338 ; , s. 403-
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Konferensbidrag (refereegranskat)abstract
- The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM will shorten the test time, but it costs large silicon area to implement it. Hence, it is important to have an efficient TAM with minimal required hardware overhead. We propose a technique that makes use of the existing bus structure with additional buffers inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. We have implemented a Tabu search based technique to optimize our test architecture, and the experimental results indicate that it produces high quality results at low computational cost.
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| 4. |
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| 5. |
- Wu, Dong, et al.
(författare)
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Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction
- 2005
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Ingår i: 8th Euromicro Conference on Digital System Design DSD2005,2005. - Porto, Portugal : IEEE Computer Society Press. - 0769524338 ; , s. 34-
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Konferensbidrag (refereegranskat)abstract
- Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to achieve comparable energy saving to that obtained using combined DVS and ABB scheme through a co-synthesis methodology which is aware of the tasks' power-composition profile (the ratio of the dynamic power to the leakage power). In particular, the presented methodology performs a power management selection at the architectural level, i.e., it decides upon which processing elements to be equipped with which power management scheme (DVS, ABB, or combined DVS and ABB) - with the aim to achieve high energy savings at a reduced implementation cost. The proposed technique maps, schedules, and voltage scales applications specified as task graphs with timing constraints. Detailed experiments including a real-life benchmark are conducted to demonstrate the effectiveness of the proposed methodology.
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