| 1. |
- Andersson, Ola, et al.
(författare)
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A differential DAC architecture with variable common-mode level
- 2002
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Ingår i: Proc. 2002 IEEE Int. Symp. on Circuits and Systems, ISCAS'02. - 0780374487 ; , s. I-113-I-116
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Konferensbidrag (refereegranskat)abstract
- A differential current-steering digital-to-analog converter (DAC) architecture allowing the common-mode level of the input signal to be varied is presented. Simulation results with models of different DAC nonlinearities indicate that the proposed architecture has a potential of improving the linearity of the converters.
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| 2. |
- Elbornsson, Jonas, et al.
(författare)
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Measurement verification of estimation method for time errors in a time-interleaved A/D converter system
- 2002
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Ingår i: Proceedings of the 2002 IEEE International Symposium on Circuits and Systems. - 0780374487 ; , s. 129-132 vol.3
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Konferensbidrag (refereegranskat)abstract
- A previously presented method for estimation of time errors in time-interleaved A/D converter systems is here verified on measurements from a dual A/D converter system. The advantage of this estimation method, compared to other methods, is that it does not require any knowledge about the input signal. The estimation is most accurate for slowly varying input signals but the signal quality is improved even when the estimation is done for a sinusoidal signal close to the Nyquist frequency.
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| 3. |
- Hägglund, Robert, 1975-, et al.
(författare)
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A polynomial-based division algorithm
- 2002
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Ingår i: IEEE Int. Symp. Circuits and Systems, 2002. - 0780374487 ; , s. III-571-III-574
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Konferensbidrag (refereegranskat)abstract
- A polynomial-based division algorithm and a corresponding hardware structure are proposed. The proposed algorithm is shown to be competitive to other conventional algorithms like the Newton-Raphson algorithm for up to about 32 bits accuracy. For example, using Newton-Raphson with less than 12 bits accuracy of the initial approximation, requires 33% more general multiplications than the proposed algorithm, in order to achieve 24 bits accuracy.
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| 4. |
- Jakonis, Darius, 1974-, et al.
(författare)
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A 1 GHz linearized CMOS track-and-hold circuit
- 2002
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Ingår i: IEEE International Symposium on Circuits and Systems, 2002. - 0780374487 ; , s. 577-580
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Konferensbidrag (refereegranskat)abstract
- A simple solution for linearization of the MOS sampling switch is proposed. It improves the SFDR of a T/H circuit and is suitable for high-speed applications. Sampling at a constant gate-source voltage minimizes sampling errors due to variable MOS sampling switch ON-conductance and channel charge injection, and also eliminates input-dependent sampling instant variation. The proposed linearized T/H circuit is fabricated in a 0.35-μm CMOS process. Test measurements show the sampling of a 1 GHz signal.
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| 5. |
- Kerttu, Mikael, et al.
(författare)
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Switching activity estimation of finite state machines for low power synthesis
- 2002
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Ingår i: Proceedings. - Piscataway, NJ : IEEE Communications Society. - 0780374487 ; , s. 65-68
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Konferensbidrag (refereegranskat)abstract
- A technique for computing the switching activity of synchronous finite state machine (FSM) implementations including the influence of temporal correlation among the next state signals is described. The approach is based upon the computation that a FSM is in a given state which, in turn, is used to compute the conditional probability that a next state bit changes given its present state value. All computations are performed using decision diagram (DD) data structures. As an application of this method, the next state activity information is utilized for low power optimization in the synthesis of binary decision diagram (BDD) mapped circuits. Experimental results are presented based on a set of the ISCAS89 sequential benchmarks showing an average power reduction of 40 percent and tip to 90 percent reduction for individual benchmarks on the estimated power dissipation.
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| 6. |
- Landernäs, Krister, et al.
(författare)
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Digit-serial implementation of LDI/LDD allpass filters
- 2002
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Ingår i: Proc. 2002 IEEE Int. Symp. on Circuits and Systems, ISCAS'02. - 0780374487 ; , s. II-684-II-687
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Konferensbidrag (refereegranskat)abstract
- In this paper we study digit-serial implementation of the general-order lossless discrete integrator/differentiator (LDI/LDD) allpass filter structure. In low-power filter implementation, digit-serial computation has been shown to be advantageous compared to bit-serial and parallel arithmetics. The digit-serial processing elements are obtained using unfolding techniques. The implementation is compared to a corresponding wave digital (WD) implementation. It is shown in an example that a WD realization requires about 60% and 30% more D flip-flops for pipelining and shimming delays, respectively, than the corresponding LDI/LDD implementation. We also study the sample period of the second-order LDI/LDD allpass filter using different digit sizes and conclude that when the filter is scheduled over a number of sample periods we achieve the shortest sample period.
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| 7. |
- Lixin, Yang, et al.
(författare)
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A non-feedback multiphase clock generator
- 2002
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Ingår i: 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353). - 0780374487 ; , s. 389-392
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Konferensbidrag (refereegranskat)abstract
- This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz
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| 8. |
- Shi, Bo, et al.
(författare)
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A 57-dB image band rejection CMOS GmC polyphase filter with automatic frequency tuning for Bluetooth
- 2002
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Ingår i: IEEE International Symposium on Circuits and Systems, 2002. ISCAS 2002.. - 0780374487 ; 5, s. 169-172
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Konferensbidrag (refereegranskat)abstract
- A 7th order polyphase G/sub -m/C IF filter with automatic frequency tuning, implemented in a 0.35/spl mu/m CMOS process, is presented. The filter has a center frequency of 3MHz and a passband of 1MHz. The image band rejection is higher than 57dB, the stop band attenuation is at least 40dB. The in-band spurious free dynamic range is around 53dB. On-chip automatic frequency tuning provides more than 240% center frequency range (i.e., 1.6MHz-3.9MHz) of the filter. The filter is well suited for employment in the Bluetooth short-range radio.
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| 9. |
- Wernersson, Lars-Erik, et al.
(författare)
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Circuits and devices with integrated VFETs and RTDs
- 2002
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Ingår i: 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353). - 0780374487 ; , s. 205-208
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Konferensbidrag (refereegranskat)abstract
- We have realised a new technology for the integration of VFETs and RTDs. For these tunnelling transistors (so called resonant tunnelling permeable base transistors) we have developed large signal models which have been implemented in a Cadence simulation environment. The DC I-V characteristics are reproduced to a very high degree in these models. The models are further used for simulations of the behaviour of simple small-scale circuits including resonant tunnelling transistors. Examples of circuits studied are a monostable-bistable logic element and a ternary quantiser, where the later is based on a new 3D architecture of RTDs and VFETs
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