| 1. |
- Andrijevic, Goran, et al.
(författare)
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A fully integrated low-IF DVB-T receiver architecture
- 2004
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Ingår i: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS. - 0780385586 ; , s. 189-192
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Konferensbidrag (refereegranskat)abstract
- We propose a fully integrated DVB-T receiver architecture for low cost CMOS implementation. The receiver uses a dual-IF architecture to cover the receive bands from 170 MHz to 862 MHz and a Low-IF of 4.57 MHz. Key performance values meet the DVB-T requirements with competitive performance (Sensitivity 72.5 dBm, Noise Figure 66 dB, Adjacent Channel Protection Ratio-ACPR=43dB, available SNR=28 dB) and suggest that low cost receivers are realistic in volume for the coming digital broadcasting systems.
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| 2. |
- Liu, Jian, et al.
(författare)
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Global routing for multicast-supporting TDM network-on-chip
- 2004
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Ingår i: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS. - NEW YORK : IEEE. - 0780385586 ; , s. 17-20
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Konferensbidrag (refereegranskat)abstract
- This paper presents a circuit-switched network architecture for Network-on-Chip. It uses the time-division-multiplexing (TDM) scheme to realize the circuits. The global routing (slot assignment at each switch) is done centrally, while the slot mapping is done locally by the switches. The switches support multicast operation, which enables multicast traffic. Furthermore, the delay in the network is predictable before a circuit is established and in-order data delivery is guaranteed
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| 3. |
- Ofner, Erwin, et al.
(författare)
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SoC-Mobinet, R&D and Education in System-on-Chip Design
- 2004
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Ingår i: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS. - 0780385586 ; , s. 77-80
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Konferensbidrag (refereegranskat)abstract
- With fabrication technologies enabling the integration of a billion transistors and allowing gigahertz frequencies, complex systems (System-on-Chip, SoC) can be realized on a single die. The design of such systems provides tremendous challenges to industry and academia. Universities need to invest a huge effort to restructure their related engineering curricula, which is only possible in close co-operations with industry and other Universities. This paper describes a project, co-funded by the European Commission and by industry, where in a joint effort related research results are turned into course contents for SoC-curricula and industry training activities.
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| 4. |
- Weerasekera, Roshan, et al.
(författare)
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Crosstalk immune interconnect driver design
- 2004
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Ingår i: 2004 International Symposium On System-On-Chip, Proceedings. - 0780385586 ; , s. 139-142
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Konferensbidrag (refereegranskat)abstract
- The effect of crosstalk noise becomes increasingly significant as geometries continue to shrink into the deep sub-micrometer regime and clock frequency increases into the multi GHz domain. Dynamic delay caused by coupling capacitance between adjacent interconnections is a critical problem, as it cannot accurately be estimated in static timing analysis. This paper presents a new driver circuit scheme called the Crosstalk Immune Interconnect Driver (XTIID), for capacitively coupled interconnects, which eliminates pattern-dependent coupling noise. Also, such an interconnect drive technology has the potential to facilitate the dynamic timing problem in deep submicrometer VLSI design.
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