| 1. |
- Duo, Xinzhong, et al.
(författare)
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On-chip versus off-chip passives analysis in radio and mixed-signal system-on-package design
- 2004
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Ingår i: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04). - NEW YORK : IEEE. - 0780386205 ; , s. 109-116
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Konferensbidrag (refereegranskat)abstract
- Advances of VLSI and packaging technologies enable condensed integration of system level functions in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP, and eliminate constraints between chip and package, a complete solution is needed to co-design and co-optimize chip and package in a total design plan with precise trade-offs of on-chip versus off-chip passives. In this paper, we present a complete and systematic design methodology for RF SoP/SoC. This methodology includes early analysis and design implementation. This early analysis is to estimate the performance and cost of each solution quickly and quantitively. Then, the best solution is found and implemented. For a better presentation, the method and design techniques are demonstrated through the design of a common emitter low noise amplifier (LNA) for 5GHz wireless LAN (local area network). Analytical equations of noise figure and transducer gain for the LNA with lossy package are also developed.
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| 2. |
- Liu, Wei, et al.
(författare)
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Thermal-issues for design of high power SiC MESFETs
- 2004
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Ingår i: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04). - NEW YORK : IEEE. - 0780386205 ; , s. 331-335
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Konferensbidrag (refereegranskat)abstract
- Silicon carbide (SiC) power MESFETs have found application in RF source and power amplifiers for wireless telecommunication systems, phased-array radar systems, and other applications. SiC MESFETs can handle much higher power than silicon and gallium arsenide power devices, due to its superior material properties, including high critical electrical field, high electron saturation velocity, and high thermal conductivity. Despite the high thermal conductivity of the material, SiC power devices may suffer from severe self-heating when operating at very high power levels. In this report, the effect of self-heating on DC performance of SiC MESFETs with 1, 2, and 3 gate fingers were studied through 2D electro-thermal simulations using ISE-TOAD. The reduction in drain current caused by self-heating was found to be more prominent for transistors with more fingers and it imposes a limitation on both the output power and the power density (in W/mm) of multi-fingered large area devices. Thermal simulations have been performed using FEMLAB to predict the junction temperature of a MESFET with 1.5 mm gate periphery and a power dissipation of 4.5 W. Three different finger layouts were examined in terms of junction temperature, yield, and the ease and cost for fabrication of the devices. Thermal simulations were also done for a larger area MESFET with a gate periphery of 12 mm and power dissipation as high as 36 W. Three different ways to place the unit cell were studied. The effect of the thermal resistance between the die backside and the environment on the junction temperature was analyzed. The thermal resistance of the die itself was deduced. It was found that the packaging thermal resistance is usually much larger than the die thermal resistance. A couple of useful ways to reduce the packaging thermal resistance and the self-heating are also discussed.
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| 3. |
- Shen, Meigen, et al.
(författare)
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Chip-package co-design for high performance and reliability off-chip communications
- 2004
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Ingår i: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04). - NEW YORK : IEEE. - 0780386205 ; , s. 31-36
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Konferensbidrag (refereegranskat)abstract
- Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design methodology is presented. We address high performance and reliability enhancement for off-chip communications under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, it is shown that the system-level performances such as signal integrity, bandwidth, and reliability are significantly improved through this co-design methodology.
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| 4. |
- Zheng, Li-Rong, et al.
(författare)
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Design and implementation of system-on-package for radio and mixed-signal applications
- 2004
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Ingår i: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04). - NEW YORK : IEEE. - 0780386205 ; , s. 97-104
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Konferensbidrag (refereegranskat)abstract
- Emerging wireless applications for logistics, intelligent home networks, smart dusts, wireless body area networks (WBAN) will need integration and fusion of a diversity of technologies, which may include digital CMOS circuits, analog/RF circuits, sensors/MEMS, embedded software and memories, antenna, displays, polymer, packaging and interconnections, new materials and new integration process. System-on-package (SoP) is considered as a promising solution for the fundamental integration platform for such applications. In this paper, we show how SoP technology can address the integration platform for these applications and how this can be done in a better way than system-on-chip integration. We first demonstrate the integration process of, SoP in liquid-crystal polymer materials. We see that liquid-crystal-polymer is a promising material for low cost RF SoP. We then demonstrate some design examples. The first one is an integrated 5GHz RF receiver front-end in liquid crystal polymer. Due to high quality of passive components in SoP, superior RF performance is found in this module. In the second example, we address several critical design issues for on-chip versus off-chip passives in a multi-band multi-standard radio for beyond 3G applications. We find that not only RF performance can be improved. Cost benefits are also obvious for such a complex radio. Chip-package co-design for smart parasitic absorption is demonstrated through an RF module for an ultrawide band radio in gigabit wireless. Concept of a SoP pacemaker in a WBAN is shown. Finally, we discuss some system level integration issues and we show how a system can be smartly partitioned for SoP so that we can obtain an optimal total solution for low-cost and good-performance wireless integration.
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