| 1. |
- Cijvat, Pieternella, et al.
(författare)
-
A 2.4 GHz CMOS power amplifier using internal frequency doubling
- 2005
-
Ingår i: 2005 IEEE International Symposium On Circuits And Systems (Iscas), Vols 1-6, Conference Proceedings. - Kobe, Japan : IEEE Press. - 0780388348 ; , s. 2683-2686
-
Konferensbidrag (refereegranskat)abstract
- A fully integrated 0.18 μm 1P6M CMOS power amplifier using internal frequency doubling is presented. Two chips were measured, one stand-alone PA and one PA with a VCO on the same chip. Since the PA and VCO operate at different frequencies, this configuration is suitable for direct-upconversion or low-IF upconversion since oscillator pulling is reduced. The maximum output power is 15 dBm, and the maximum drain efficiency is 10.7% at an output operating frequency of 2.4 GHz
|
|
| 2. |
- Dubrova, Elena
(författare)
-
Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs
- 2005
-
Ingår i: 2005 IEEE International Symposium On Circuits And Systems (ISCAS), Conference Proceedings. - : IEEE. - 0780388348 ; , s. 2212-2215
-
Konferensbidrag (refereegranskat)abstract
- Simulation-based verification is a popular method for functional validation of hardware. It is performed by applying a set of tests to the system under consideration and to its reference model, and comparing the results. The effectiveness of a test suite is measured by the fraction of the system covered by the tests. In this paper, we present a technique for selecting a part of the system, called checkpoints, with the property that any set of tests which covers the checkpoints covers the entire system. Thus, by constructing a test suit for the checkpoints, a 100% coverage can be achieved. We present a linear-time algorithm for computing a minimum checkpoint set based on pre- and post-dominator relations of the control flow graph of the HDL program representing the system.
|
|
| 3. |
- Duo, Xinzhong, et al.
(författare)
-
A concurrent multi-band LNA for multi-standard radios
- 2005
-
Ingår i: 2005 IEEE International Symposium On Circuits And Systems (ISCAS), Conference Proceedings. - : IEEE. - 0780388348 ; , s. 3982-3985
-
Konferensbidrag (refereegranskat)abstract
- A source-degenerated cascade LNA, which works at 2.4GHz and 5.8GHz simultaneously, is designed for Bluetooth and IEEE wireless LAN 802.11 a/b/g receivers. In this design, 0.15 mu m GaAs PHEMT technology and embedded passives in MCM-D substrate are implemented. At 2.4GHz and 5.8GHz, this LNA provides 12.2dB and 15.3dB gain, respectively. Noise figures of the LNA are 0.53dB and 1.43dB, respectively. Good input matching and output matching are also achieved-S11 and S22 at both frequencies are less than -10dB.
|
|
| 4. |
- Edman, F, et al.
(författare)
-
A scalable pipelined complex valued matrix inversion architecture
- 2005
-
Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS). - 0780388348 ; , s. 4489-4492
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R-1 with Q. We show that traditional triangular array architectures employing O(n2) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system
|
|
| 5. |
- Guo, Zhan, et al.
(författare)
-
A 53.3 Mb/s 4x4 16-QAM MIMO Decoder in 0.35um CMOS
- 2005
-
Ingår i: IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005.. - 0780388348 ; 5, s. 4947-4950
-
Konferensbidrag (refereegranskat)abstract
- An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4/spl times/4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-/spl mu/m CMOS technology. The chip core area is 5.76 mm/sup 2/ with 91 K gates. Furthermore, the decoding throughput that the chip can support is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The corresponding decoding latency is 2.4 /spl mu/s.
|
|
| 6. |
- Hedberg, Hugo, et al.
(författare)
-
A low complexity architecture for binary image erosion and dilation using structuring element decomposition
- 2005
-
Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS). - 0780388348 ; , s. 3431-3434
-
Konferensbidrag (refereegranskat)abstract
- This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log2(SEheight), which means that a large span of SE sizes can be supported with a small amount of hardware
|
|
| 7. |
- Kamuf, Matthias, et al.
(författare)
-
Area and power efficient trellis computational blocks in 0.13μm CMOS
- 2005
-
Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS). - 0780388348 ; , s. 344-347
-
Konferensbidrag (refereegranskat)abstract
- Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption
|
|
| 8. |
- Piper, Johan, et al.
(författare)
-
Design considerations of a floating-point ADC with embedded S/H
- 2005
-
Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS). - 0780388348 ; , s. 6166-6169
-
Konferensbidrag (refereegranskat)abstract
- This paper presents the implementation and test results of a 10+5 bit 50 MS/s floating-point ADC, along with the design considerations. The combination of resistive weighting with identical chopped gain stages proved successful in gain, delay and offset matching. It demonstrated that the input referred thermal noise of the gain stages needs to aim for 15 bits, while the rest of the requirements such as channel matching (gain, delay, offset) and settling time need only 10 bits. The channel selecting logic has a serious impact on the ADC distortion, especially at high frequencies. For this reason, a robust channel selecting logic is suggested
|
|
| 9. |
- Rodrigues, Joachim, et al.
(författare)
-
A dual-mode wavelet based R-wave detector using single-Vt for leakage reduction [cardiac pacemaker applications]
- 2005
-
Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS). - 0780388348 ; , s. 1330-1333
-
Konferensbidrag (refereegranskat)abstract
- This paper presents the implementation of a dual mode wavelet based R-wave detector for cardiac pacemakers. A previously published R-wave detector was developed for a noisy environment. This detector has been supplemented with a noise detector that operates in supervision mode, and automatically activates/deactivates 2/3 of the detector hardware without performance degradation. The noise detection is based on zero-crossing rate computation. A low clock frequency results in leakage power being the main power source. Power estimation shows that the power consumption in an ASIC is reduced by 67% when using gate-transistors in the power supply rails. The detector has been synthesized in 0.13 μm low-leakage CMOS technology
|
|
| 10. |
- Svensson, Henrik, et al.
(författare)
-
Implementation aspects of a novel speech packet loss concealment method
- 2005
-
Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS). - 0780388348 ; , s. 2867-2870
-
Konferensbidrag (refereegranskat)abstract
- A speech data packet loss concealment algorithm based on pitch period repetition is presented and a novel low complexity method to refine a pitch period estimate is introduced. Objective performance measurements show that this pitch refinement improves the quality of packet loss concealment. Hardware-software codesign techniques have been investigated to implement the algorithm. Using a coprocessor approach, a processing delay of 0.9 ms and a overall speedup of 3.3 was achieved
|
|
