| 1. |
- Ahmad, Waqar, et al.
(författare)
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Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairs
- 2012
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 73:1, s. 311-328
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Tidskriftsartikel (refereegranskat)abstract
- In this article we propose an efficient and accurate model to estimate peak-to-peak core switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of dies interconnected through TSVs. The proposed model is accurate with only a 2–3% difference in peak-to-peak core switching noise as compared to the Ansoft Nexxim4.1 equivalent model. The proposed model is 3–4 times faster than Ansoft Nexxim4.1 and uses two times less memory as compared to the Ansoft Nexxim4.1 equivalent model. In this article we also thoroughly establish design guidelines for almost flat output impedance magnitude at each stage of a vertical chain of power distribution TSV pairs to realize a resonance free scenario over a wide operating frequency range. We also establish decoupling capacitance design guidelines based on the optimum output impedance and critically damped supply voltage for the core logic for each stage of a vertical chain of power distribution TSV pairs.
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| 2. |
- Ahsan, Naveed, et al.
(författare)
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A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS
- 2012
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Ingår i: Analog Integrated Circuits and Signal Processing. - : SpringerLink. - 0925-1030 .- 1573-1979. ; 70:1, s. 79-90
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.
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| 3. |
- Ahsan, Naveed, 1974-, et al.
(författare)
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A Design Approach for Flexible RF Circuits Using Reconfigurable PROMFA Cells
- 2009
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Ingår i: Analog Integrated Circuits and Signal Processing. - 0925-1030 .- 1573-1979.
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)abstract
- This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.
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| 4. |
- Andersson, Mattias, et al.
(författare)
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Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
- 2013
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 76:3, s. 353-366
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a 3rd-order, 3-bit continuous-time (CT) \Updelta\Upsigma Δ Σ modulator for an LTE radio receiver. A return-to-zero (RZ) pulse, centered in the sampling period by a quadrature clock, is used in the innermost DAC to reduce the sensitivity to loop-delay variations in the modulator, and omit implementing the additional loop delay compensation usually needed in CT modulators. The performance and stability of the NRZ/NRZ/RZ feedback scheme is thoroughly analysed using a discrete-time model. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 × 0.4 mm2. It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, and a power consumption of 7.5 mW from a 1.2 V supply.
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| 5. |
- Andersson, Niklas, et al.
(författare)
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Models and Implementation of a Dynamic Element Matching DAC
- 2003
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Ingår i: Analog Integrated Circuits and Signal Processing. - Netherlands : Springer. - 0925-1030 .- 1573-1979. ; 34:1, s. 7-16
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Tidskriftsartikel (refereegranskat)abstract
- The dynamic element matching (DEM) techniques for digital-to-analog converters (DACs) has been suggested as a promising method to improve matching between the DAC''s reference levels. However, no work has so far taken the dynamic effects that limit the performance for higher frequenciesinto account. In this paper we present a model describing the dynamic properties of a DEM DAC and compare the simulated results with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35-μm CMOS process. The measured data agrees well with the results predicted by the used model. It is also shown that the DEM technique does not necessarily increase the performance of a DAC when dynamic errors are dominating the achievable performance.
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| 6. |
- Andersson, Stefan, et al.
(författare)
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An Active Recursive RF Filter in 0.35 μm BiCMOS
- 2005
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Ingår i: Journal of Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 44:3, s. 213-218
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Tidskriftsartikel (refereegranskat)abstract
- An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is −26 and −34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.
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| 7. |
- Andersson, Stefan, et al.
(författare)
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SC Filter for RF Sampling and Downconversion with Wideband Image Rejection
- 2006
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Ingår i: Journal of Analog Integrated Circuits and Signal Processing by Springer, special issue: MIXDES. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 49:2, s. 115-122
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Tidskriftsartikel (refereegranskat)abstract
- In this paper we present an SC filter for RF downconversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.13μm CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included.
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| 8. |
- Andreani, Pietro, et al.
(författare)
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A 2.4-GHz CMOS monolithic VCO with an MOS varactor
- 2000
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Ingår i: Analog Integrated Circuits and Signal Processing. - 0925-1030. ; 22:1, s. 17-24
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Tidskriftsartikel (refereegranskat)abstract
- A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8 mu m CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about -118 dBc/Hz at 1 MHz from the carrier.
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| 9. |
- Andreani, Pietro, et al.
(författare)
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A chip for linearization of RF power amplifiers using predistortion based on a bit-parallel complex multiplier
- 2000
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Ingår i: Analog Integrated Circuits and Signal Processing. - 0925-1030. ; 22:1, s. 25-30
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 mu m CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption.
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| 10. |
- Andreani, Pietro, et al.
(författare)
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A digitally controlled shunt capacitor CMOS delay line
- 1999
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Ingår i: Analog Integrated Circuits and Signal Processing. - 0925-1030. ; 18:1, s. 89-96
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Tidskriftsartikel (refereegranskat)abstract
- Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 x 0.5 ns delay under large temperature, supply voltage, and technological process quality variations.
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