| 1. |
- Andersson, Henrik, et al.
(författare)
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System of nano-silver inkjet printed memory cards and PC card reader and programmer
- 2011
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Ingår i: Microelectronics Journal. - : Elsevier BV. - 0959-8324 .- 0026-2692. ; 42:1, s. 21-27
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Tidskriftsartikel (refereegranskat)abstract
- This work describes the development of inkjet printed, low-cost memory cards, and complementary pair of memory card reader and card reader/programmer for PCs. This constitutes a complete system that can be used for various applications. The memory cards are manufactured by inkjet printing nano-silver ink on photo paper substrate. The printed memory structures have an initial high resistance that can later be programmed to specific values representing data on the cards, the so called Write Once Read Many (WORM) memories. The memory card reader measures the resistance values of the memory cells and reads it back to the computer by USB connection. Using multiple resistance levels that represent different states it is possible to have a larger number of selectable combinations with fewer physical bits compared to binary coding. This somewhat counters one of the limitations of resistive memory technology that basically each cell needs one physical contact. The number of possible states is related to the resolution of the reader and the stability of the WORM memory.
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| 2. |
- Chouhan, Shailesh, et al.
(författare)
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A 352nW, 30 ppm/°C all MOS nano ampere current reference circuit
- 2017
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Ingår i: Microelectronics Journal. - : Elsevier. - 0959-8324 .- 0026-2692. ; 69, s. 45-52
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Tidskriftsartikel (refereegranskat)abstract
- In this work, an ultra low power all-MOSFET based current reference circuit, developed in 0.18 µm CMOS technology, is presented. The proposed circuit is based on the classical resistor-less beta multiplier circuit with an additional temperature compensation feature. The circuit is capable of providing the reference current in a nanoampere range for the supply voltage ranging from 1 V to 2 V in the industrial temperature range of −40 °C to 85 °C. The measurements were performed on 10 prototypes. The measured mean value of the reference current is 58.7 nA with a mean temperature coefficient value of 30 ppm/°C. In addition, the measured mean line regulation is 3.4%/V in the given supply voltage range. The total current consumption of the circuit is 352 nA and the chip area is 0.036 mm2.
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| 3. |
- Iwata, H., et al.
(författare)
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A new type of quantum wells : Stacking faults in silicon carbide
- 2003
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Ingår i: Microelectronics Journal. - 0026-2692. ; 34:5, s. 371-374
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- We report on a new type of quantum wells with the width as thin as 10Å, which are composed of SiC only, and consequently have ideal interfaces. These quantum wells are actually stacking faults in SiC. Certain types of stacking faults in SiC polytypes create small 3C-like regions, where the stacking sequences along the c-axis become locally cubic in the hexagonal host crystals. Since the conduction band offsets between the cubic and hexagonal polytypes are very large with the conduction band minima of 3C-SiC lower than that of the other polytypes, such thin 3C inclusions can introduce locally lower conduction bands, thus acting as quantum films perpendicular to the c-axis. One mechanism for the occurrence of stacking faults in the perfect SiC single crystals is the motion of partial dislocations in the basal planes, the partial dislocations leaving behind stacking fault regions. © 2003 Elsevier Science Ltd. All rights reserved.
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| 4. |
- Jalili, Armin, et al.
(författare)
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Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs
- 2011
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Ingår i: Microelectronics Journal. - Oxford, UK : Elsevier. - 0959-8324 .- 0026-2692. ; 42:1, s. 158-164
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a digital background calibration technique to compensate inter-channel gain and offset errors in parallel, pipelined analog-to-digital converters (ADCs). By using an extra analog path, calibration of each ADC channel is done without imposing any changes on the digitizing structure, i.e., keeping each channel completely intact. The extra analog path is simplified using averaging and chopping concepts, and it is realized in a standard 0.18‐μm CMOS technology. The complexity of the analog part of the proposed calibration system is same for a different number of channels.Simulation results of a behavioral 12-bit, dual channel, pipelined ADC show that offset and gain error tones are improved from −56.5 and −58.3 dB before calibration to about −86.7 and −103 dB after calibration, respectively.
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| 5. |
- Karpyna, V A, et al.
(författare)
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Electron field emission from ZnO self-organized nanostructures and doped ZnO : Ga nanostructured films
- 2009
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Ingår i: Microelectronics Journal. - : Elsevier BV. - 0959-8324 .- 0026-2692. ; 40:2, s. 229-231
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Tidskriftsartikel (refereegranskat)abstract
- Self-organized ZnO nanostructures were grown by thermal decomposition of metalorganic precursors as well as by carbothermal reduction process. Nanostructured undoped and gallium-doped ZnO nanostructured films were deposited by plasma-enhanced chemical vapor deposition from metalorganic compounds. Electron field emission follows Fowler-Nordheim equation. Efficient electron emission was obtained from self-organized nanorstructures due to their geometric shape. Enhanced field emission from ZnO:Ga nanorstructured films in comparison with undoped ZnO films is obliged to lowering work function at doping by gallium.
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| 6. |
- Khan, Sajid, et al.
(författare)
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An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications
- 2019
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Ingår i: Microelectronics Journal. - : Elsevier. - 0959-8324 .- 0026-2692. ; 92
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Tidskriftsartikel (refereegranskat)abstract
- Physically Unclonable Functions (PUF) have emerged as security primitives which can generate high entropy, temper resilient bits for security applications. However, the power budget of the ring oscillator (RO) PUF limits the use of RO PUF in IoT applications, in this concern a low power variant of RO PUF is much needed. In this paper, we have presented an ultra-low power, lightweight, configurable RO PUF based on the 4T XOR architecture. The proposed architecture is aging resilient; hence it produces a stable PUF output over the years. Also, it has a large number of challenge-response-pair (CRP) compared to the other architectures, which makes it suitable for chip identification as well as cryptographic key generation. The proposed PUF is implemented on 40 nm CMOS technology, and for the validation of design, we have also implemented on FPGA. The simulation results show that it has a uniqueness of 0.489 and worst-case reliability of 96.43% and 93.15% at 125 °C and 1.2 V, respectively. Compared to the conventional RO PUF it consumes 98.06% and 95.47% less dynamic and leakage power, respectively.
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| 7. |
- Li, Jian-De, et al.
(författare)
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Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips
- 2019
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Ingår i: Microelectronics Journal. - : Elsevier. - 0959-8324 .- 0026-2692. ; 83, s. 185-196
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Tidskriftsartikel (refereegranskat)abstract
- Digital microfluidic biochips (DMFBs) facilitate modern healthcare applications. One of the most important applications is point-of-care (POC) clinical diagnosis which is directly related to human health. However, biochemical experiments are usually error-prone, which makes monitoring intermediate results during bioassay execution be required to ensure the correctness of POC clinical diagnosis. To tackle this problem, cyber-physical digital microfluidic biochips with integrated sensors have been proposed and have attracted attention recently. In order to fully utilize the sensors for detection, the reusability of sensors should be taken into consideration during the module placement stage of cyber-physical DMFBs synthesis flow. Moreover, excessive actuation of electrodes may cause reliability degradation and this issuse should also be taken care of during module placement stage. In order to deal with the aforementioned problems, this paper presents the first co-optimization method for both module and sensor placement. Experimental results show that the proposed method can effectively minimize bioassay completion time while meeting all constraints from sensors and electrodes.
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| 8. |
- Shen, Meigen, et al.
(författare)
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Robustness enhancement through chip-package co-design for high-speed electronics
- 2005
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Ingår i: Microelectronics Journal. - : Elsevier BV. - 0959-8324 .- 0026-2692. ; 36:9, s. 846-855
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Tidskriftsartikel (refereegranskat)abstract
- The low interaction between chip and package design has an increasingly limiting effect on the system performance. In this paper, the chip-package co-design flow is presented. We address robustness enhancement under the package and interconnection constraints as well as process, voltage, and temperature (PVT) variations by using impedance control, optimal pins assignment and transmitter equalization. From the simulation results we find that without on-chip digital compensation circuit, the variation of the driver's output impedance is 37% under different PVT conditions. However, it is only 5% when digital compensation circuit is used. Through optimal pins assignment the effective inductance of the pins is reduced. When power and ground pins are used as shielding pins, crosstalk is also decreased by 10 dB. Transmitter equalization effectively decreases inter-symbol interference caused by interconnection attenuation and dispersion. In our design example we find that without equalization the eye-diagram is almost closed at the receiver end. On the other hand with one-tap pre-emphasis equalization the eye-diagram is open and has a height of 90 mV and a width of 140 ps. It is also found that there is a clear optimal window for high data rate in this design. Without a chip-package co-design such an optimal window will not be found.
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| 9. |
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