| 1. |
- Strak, Adam, et al.
(författare)
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Power-supply and substrate noise-induced timing jitter in nonoverlapping clock generation circuits
- 2008
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268 .- 1549-8328 .- 1558-0806. ; 55:4, s. 1041-1054
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Tidskriftsartikel (refereegranskat)abstract
- This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mu m CMOS process parameters, and a reference simulation in 0.18 mu m is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mu m process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.
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| 2. |
- Alty, S. R., et al.
(författare)
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Efficient time-recursive implementation of matched filterbank spectral estimators
- 2005
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - 1057-7122 .- 1558-1268. ; 52:3, s. 516-521
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a computationally efficient sliding window time updating of the Capon and amplitude and phase,estimation (APES) matched filterbank spectral estimators based on the time-variant displacement structure of the data covariance matrix. The presented algorithm forms a natural extension of the most computationally efficient algorithm to date, and offers a significant computational gain as compared to the computational complexity associated with the batch re-evaluation of the spectral estimates for each time-update. Furthermore, via simulations, the algorithm is found to be numerically superior to the time-updated spectral estimate formed from directly updating the data covariance matrix.
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| 3. |
- Alzaher, H., et al.
(författare)
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A CMOS fully balanced four-terminal floating nullor
- 2002
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268. ; 49:4, s. 413-424
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents design and implementation of a CMOS fully balanced realization of the four-terminal floating nullor (FTFN). The proposed fully balanced FTFN (FBFTFN) is an essential building block for implementing fully balanced architectures of both voltage and current-mode analog CMOS integrated circuits (ICs). A low-power class AB CMOS realization of the proposed circuit is fabricated in a 1.2-mum technology. The proposed circuit has numerous applications. Several applications including fully balanced amplifiers, filters, and sinusoidal oscillators are presented. All proposed design techniques and circuits are experimentally verified.
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| 4. |
- Ben Dhaou, I., et al.
(författare)
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Current mode, low-power, on-chip signaling in deep-submicron CMOS technology
- 2003
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268. ; 50:3, s. 397-406
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Tidskriftsartikel (refereegranskat)abstract
- qThis paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10% Experimental results on a set of benchmark signaling problems implemented in a 0.25-mum 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a twofold reduction in the power and a reduction of 1.4 times the area.
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| 5. |
- Elbornsson, Jonas, et al.
(författare)
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Analysis of Mismatch Effects in Randomly Interleaved A/D Converter System
- 2005
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268. ; 52:3, s. 465-476
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Tidskriftsartikel (refereegranskat)abstract
- To significantly increase the sampling rate of an A/D converter (ADC), a time interleaved ADC system is a good option. The drawback of a time interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain and offset mismatch errors are introduced in the ADC system. These errors cause non harmonic distortion in the sampled signal. One way to decrease the impact of the mismatch errors is to spread the distortion over a wider frequency range by randomizing the order in which the ADCs are used in the interleaved structure. In this paper we analyze how the spectrum is affected by mismatch errors in a randomly interleaved ADC system. We also discuss how the mismatch errors can be estimated.
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| 6. |
- Elbornsson, Jonas, et al.
(författare)
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Blind Adaptive Equalization of Mismatch Errors in Time Interleaved A/D Converter System
- 2004
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - 1057-7122 .- 1558-1268. ; 51:1, s. 151-158
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Tidskriftsartikel (refereegranskat)abstract
- To significantly increase the sampling rate of an AID converter (ADC), a time-interleaved ADC system is a good option. The drawback of a time-interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper, we present a method for estimation and compensation of the mismatch errors. The estimation method requires no knowledge about the input signal except that it should be bandlimited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated while the ADC is running. The method is also adaptive to slow changes in the mismatch errors. The estimation method has been validated with simulations and measurements from a time-interleaved ADC system.
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| 7. |
- Harnefors, L., et al.
(författare)
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Suppression of overflow limit cycles in LDI all-pass/lattice filters
- 2000
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268. ; 47:4, s. 594-598
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Tidskriftsartikel (refereegranskat)abstract
- In this paper it is shown that zero-input overflow limit cycles can be suppressed in a class of lossless digital integrator (LDI) all-pass filters. namely, that introduced in [1], This holds for any filter order, provided that saturation overflow characteristics are used at the input of each delay and for certain restrictions for the multiplier values. The results are shown to apply also to lossless digital differentiator (LDD) filters. The restrictions of multiplier values have the effect of excluding certain combinations of poles within the unit circle, most of which are in the left half circle where corresponding LDD filters can be used. Asymptotic stability can be guaranteed for all second-order LDI and LDD filters.
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| 8. |
- Iannelli, L., et al.
(författare)
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Analysis of periodically forced uncertain feedback systems
- 2003
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268. ; 50:2, s. 244-258
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Tidskriftsartikel (refereegranskat)abstract
- Conditions for existence and stability of stationary periodic solutions of uncertain periodic systems are addressed in this paper. Existence and harmonic performance are studied using integral quadratic constraints (IQCs) defined on the space of square integrable periodic functions. Stability is investigated using IQCs defined on the usual space of square integrable functions. The analysis results in criteria formulated as affinely parameterized operator inequalities. Methods of convex optimization are used to find feasible parameters. Two applications will be discussed. The first is harmonic analysis of an electronic circuit and the second involves estimation of the amplitude of a periodic disturbance in a nonlinear control system.
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| 9. |
- Iannelli, L., et al.
(författare)
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Dither for smoothing relay feedback systems
- 2003
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268. ; 50:8, s. 1025-1035
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Tidskriftsartikel (refereegranskat)
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| 10. |
- Johansson, Håkan, 1969-, et al.
(författare)
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Least-squares and minimax design of polynomial impulse response FIR filters for reconstruction of two-periodic nonuniformly sampled signals
- 2007
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - 1057-7122 .- 1558-1268. ; 54:4, s. 877-888
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Tidskriftsartikel (refereegranskat)abstract
- This paper proposes polynomial impulse response finite-impulse response filters for reconstruction of two-periodic nonuniformly sampled signals. The foremost advantages of using these reconstruction filters are that on-line filter design thereby is avoided and subfilters with fixed dedicated multipliers can be employed in an implementation. The overall implementation cost can in this way be reduced substantially in applications where the sampling pattern changes from time to time. The paper presents two different design techniques that yield optimum filters in the least-squares and minimax senses, respectively. Design examples are included that illustrate the benefits of the proposed filters. © 2007 IEEE.
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