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Träfflista för sökning "L773:1065 514X OR L773:1563 5171 "

Sökning: L773:1065 514X OR L773:1563 5171

  • Resultat 1-8 av 8
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1.
  • Alam, Syed Asad, 1984-, et al. (författare)
  • Design of Finite Word Length Linear-Phase FIR Filters inthe Logarithmic Number System Domain
  • 2014
  • Ingår i: VLSI design (Print). - Egypt : Hindawi Publishing Corporation. - 1065-514X .- 1563-5171. ; 2014:217495
  • Tidskriftsartikel (refereegranskat)abstract
    • Logarithmic number system (LNS) is an attractive alternative to realize finite-length impulse response filters because ofmultiplication in the linear domain being only addition in the logarithmic domain. In the literature, linear coefficients are directlyreplaced by the logarithmic equivalent. In this paper, an approach to directly optimize the finite word length coefficients in theLNS domain is proposed. This branch and bound algorithm is implemented based on LNS integers and several different branchingstrategies are proposed and evaluated. Optimal coefficients in the minimax sense are obtained and compared with the traditionalfinite word length representation in the linear domain as well as using rounding. Results show that the proposed method naturallyprovides smaller approximation error compared to rounding. Furthermore, they provide insights into finite word length propertiesof FIR filters coefficients in the LNS domain and show that LNS FIR filters typically provide a better approximation error comparedto a standard FIR filter.
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2.
  • Ben Dhaou, I., et al. (författare)
  • Energy efficient signaling in deep-submicron technology
  • 2002
  • Ingår i: VLSI design (Print). - : Hindawi Limited. - 1065-514X .- 1563-5171. ; 15:3, s. 563-586
  • Tidskriftsartikel (refereegranskat)abstract
    • In deep-submicron technology, global interconnect capacitances have started reaching several orders of magnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumption of a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) the intrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chip signaling power consumption. In this paper, a scheme has been proposed for combating crosstalk noise and reducing power consumption while driving the global wire at an optimal delay. This scheme is based on reduced voltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted and resized to compensate for the speed degradation caused by scaling the supply voltage and eradicating the crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along with accurate delay and crosstalk-noise estimation algorithms for distributed RLC wires. The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical nets than does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental results show that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.
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3.
  • Bertozzi, Davide, et al. (författare)
  • Networks-on-Chip : Emerging Research Topics and Novel Ideas (Editorial)
  • 2007
  • Ingår i: VLSI design (Print). - : Hindawi Limited. - 1065-514X .- 1563-5171. ; 2007, s. ID: 26454-
  • Tidskriftsartikel (populärvet., debatt m.m.)abstract
    • Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.
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4.
  • Brennan, K.F., et al. (författare)
  • Monte Carlo modeling of wurtzite and 4H phase semiconductor materials
  • 2001
  • Ingår i: VLSI design (Print). - 1065-514X .- 1563-5171. - 0852617046 ; 13:1-4, s. 117-124
  • Tidskriftsartikel (refereegranskat)abstract
    • We present a discussion of the complexities encountered in particle simulation models for noncubic symmetry materials, focusing on the wurtzite and 4H phases of semiconductors. We have identified three general issues, band structure, scattering mechanisms, and band intersections, which in our opinion, constitute the most important modifications to Monte Carlo simulators for cubic symmetry materials. Owing to the increased number of atoms and size of the unit cell, the band structure is far more complex in wurtzite and 4H polytypes than in zincblende phase semiconductors. This added complexity is reflected by the greater number of bands, smaller Brillouin zone and concomitant increase in the number of band intersections. We have found that the band intersection points greatly influence the transport dynamics. In this paper, we discuss our initial attempts at treating transport near these points
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5.
  • Nilsson, Peter (författare)
  • Architectures and arithmetic for low static power consumption in nanoscale CMOS
  • 2009
  • Ingår i: VLSI Design. - : Hindawi Limited. - 1065-514X .- 1563-5171. ; :Article ID 749272
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative power ratio is strongly dependent on the used word length, i.e. the gain in power ratio is larger for longer word lengths. A static power ratio at 0.48 is shown for the bit-serial FIR-filter and a power ratio at 0.11 is shown in the arithmetic part of the FIR-filter. The static power ratio in the IIR-filter is 0.36 in the bit-serial filter and 0.06 in the arithmetic part of the filter. It is also shown that the use of storage, such as registers, relatively the arithmetic part affects the power ratio. The relatively lower power consumption in the IIR-filter compared to the FIR-filter is due to the lower use of registers.
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6.
  • Oelmann, Bengt, et al. (författare)
  • Automatic FSM synthesis for low-power mixed synchronous/asynchronous implementation
  • 2001
  • Ingår i: VLSI design (Print). - 1065-514X .- 1563-5171. ; 12:2, s. 167-186
  • Tidskriftsartikel (refereegranskat)abstract
    • Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into a number of coupled sub-FSMs where only the part that is involved in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a partitioning algorithm and sub-FSM synthesis to an implementation architecture. In this paper, we first introduce an implementation architecture for partitioned FSMs that uses gated-clock technique for disabling idle parts of the circuits and asynchronous controllers for communication between the sub-FSMs. We then describe a new transformation procedure for the sub-FSM. The FSM synthesis flow has been automated in a prototype tool that accepts an FSM specification. The tool generates RT-level VHDL code with identical cycle-to-cycle input/output behaviour in accordance to with the specification. An average power reduction of 45% has been obtained for a set standard FSM benchmarks.
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7.
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8.
  • Carlsson, Erik F., 1968, et al. (författare)
  • Electric field dependent microwave losses in KTaO3 single crystal with YBa2CU3O7-x electrodes
  • 1999
  • Ingår i: Ferroelectrics, Letters Section. - : Informa UK Limited. - 0731-5171 .- 1563-5228. ; 25:5-6, s. 141-152
  • Tidskriftsartikel (refereegranskat)abstract
    • We have measured the voltage dependence of the resonant frequency and the microwave losses for parallel-plate resonators based on single crystals KTaO3, with YBa2Cu3O7-x electrodes. The losses increase and the dielectric constant decrease monotonically with applied voltage. Both the dielectric constant and the losses show a hysteretic effect in the voltage dependence. The hysteretic effects may be explained by electric field assisted charge trapping both in the KTaO3, crystal and at the KTaO3/YBa2Cu3O7-x interfaces
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  • Resultat 1-8 av 8

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