| 1. |
- Abdalla, Suliman, et al.
(författare)
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Circuit Implementation of Mechanism for Charge-Sharing Suppression for Photon-Counting Pixel Arrays
- 2005
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Ingår i: 23rd NORCHIP Conference 2005. - : IEEE conference proceedings. - 1424400643 ; , s. 137-140
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Konferensbidrag (refereegranskat)abstract
- This work proposes an efficient circuit implementation of a mechanism for charge-sharing suppression in photon-counting pixel arrays based on current-mode circuits for the analog parts. The additional circuits needed for charge-sharing suppression in a four-pixel cluster, leads to an increase in power consumption of 36% and only a marginal increase in circuit area. The implemented pixel with window-discrimination, managing charge-sharing in a four-pixel cluster and with an event-counter of 13 bits, consists of 300 transistors and has a power consumption of 2.7 μW when idle. It is implemented in a 120nm CMOS process and the presented results are based on simulations.
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| 2. |
- Duo, Xinzhong, et al.
(författare)
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Broadband CMOS LNAs for IR-UWB receiver
- 2005
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Ingår i: Norchip 2005, Proceedings. - New York : IEEE. - 1424400643 ; , s. 273-276
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Konferensbidrag (refereegranskat)abstract
- Two single-ended wideband LNAs for Ultrawide-band receiver have been designed and implemented in 0.18 mu m CMOS technology. The first one, a feed-back LNA, is a two-stage amplifier with a improved feedback loop, which provides high gain and enables the input port to match with 500 in a wide frequency range from 500MHz to 8GHz. The second one, an LC low-pass-filter matched LNA, employs a third-order low pass filter in the input port to match a frequency range from 3GHz to 8GHz. In both of the LNAs, the input stage is a common source amplifier. Inductive shunt peaking is used for maximizing the bandwidth and flatting the gain. In the feed-back LNA, measurements show that the maximum gain is 11.5dB, the 3-dB; bandwidth is from 500MHz to 7GHz, IIP3 is -2.2dBm at 4GHz, the minimum noise figure is around 5.7dB, S11 is less than 8.2dB, and the power consumption is 14mW. In the LC filter matched LNA, the 3-dB bandwidth is from 3GHz to 7.3GHz. The maximum gain is 9.6dB, IIP3 is 0dBm at 4 GHz, the minimum noise figure is 7.6dB, S11 is less than -13.4dB and the power consumption is 23mW.
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| 3. |
- Holsmark, Rickard, et al.
(författare)
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Design Issues and Performance Evaluation of Mesh NoC with Regions
- 2005
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Ingår i: 23rd Norchip Conference, Oulu, Finland, November 2005. - 1424400643
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Konferensbidrag (refereegranskat)abstract
- Mesh topology is popular for Network on Chip (NoC) architectures because it has many desirable fabrication and performance properties, due to fixed sized rectangular tiles for resources. Region concept has been proposed to handle cores with larger size than the tiles. In this paper, we present an elaboration of the region concept, pointing out new design issues and possibilities. Special routing algorithms are required for deadlock free communication to handle blockage introduced by the regions. We show that fault tolerant algorithms developed for multi-computer systems can be adapted for this purpose. By simulation, we study the introduction of rectangular regions in a 7X7 NoC. Our study shows that the position and orientation of regions have a strong influence on achieved network performance.
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| 4. |
- Isoaho, J A, et al.
(författare)
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New course on computational platforms towards nanoscale systems
- 2005
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Ingår i: 23rd NORCHIP Conference 2005. - : IEEE. - 1424400643 - 9781424400645 ; , s. 226-229
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Konferensbidrag (refereegranskat)abstract
- In this paper we present an educational approach for a paradigm shift needed when changing from deep submicron CMOS designs to real nano andnanoscaletechnologies [7] in complex communication and computationsystemimplementations. Here we present an introductioncourseimplemented for starting the paradigm shift in curriculum. Here we presentcoursetargets, structure and implementation as well as future designer competence profiles. Thecourseis consisting of five thematic areas: nano-scale technologies, parallelplatforms, concurrent algorithms, reconfigurablesystemsand autonomoussystemmanagement. These thematic areas compound the core of future nanosystems educational program upgrades for current NoC curricula.
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| 5. |
- Kämpe, Andreas, et al.
(författare)
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A DVB-H receiver architecture
- 2005
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Ingår i: Norchip 2005, Proceedings. - NEW YORK : IEEE. - 1424400643 ; , s. 265-268
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Konferensbidrag (refereegranskat)abstract
- This paper proposes an integrated DVB-H receiver architecture. The main focus has been low power consumption, aiming at handheld battery operated devices. The total power consumption for the RF tuner is estimated to be less than 20 in W with a duty cycle of 10%. The receiver uses a low-IF architecture and cover the receive bands from 470 MHz to 702 MHz, with an IF of 4.57 MHz. The proposed receiver meets the DVB-H requirements. The, sensitivity is -88 dBm, the noise figure 5.7 dB and the Adjacent Channel Protection Ratio (ACPR) is -51 dB.
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| 6. |
- Lawal, Najeem, et al.
(författare)
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Embedded FPGA memory requirements for real-time video processing applications
- 2005
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Ingår i: 23rd NORCHIP Conference 2005. - : IEEE conference proceedings. - 1424400643 ; , s. 206-209
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Konferensbidrag (refereegranskat)abstract
- FPGAs show interesting properties for real-time implementation of video processing systems. An important feature is the available on-chip RAM blocks embedded on the FPGAs. This paper presents an analysis of the current and future requirements of video processing systems put on these embedded memory resources. The analysis is performed such that a set of video processing systems are allocated onto different existing and extrapolated FPGA architectures. The analysis shows that FPGAs should support multiple memory sizes to take full advantage of the architecture. These results are valuable for both designers of systems and for planning the development of new FPGA architectures
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| 7. |
- Lepistö, Niklas, et al.
(författare)
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High Performance FPGA based Camera Architecture for Range Imaging
- 2005
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Ingår i: 23rd NORCHIP Conference 2005. - : IEEE conference proceedings. - 1424400643 ; , s. 165-168
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Konferensbidrag (refereegranskat)abstract
- Range imaging is often used in classification of objects in process industry. The speed of inspection needs to be high, so it does not become the bottleneck in the process. This paper presents an FPGA based architecture for range imaging. Using centre of gravity it calculates the range positions from 2D images. The results show that the proposed architecture can process range values with a performance up to 150 Msamples per second. Thus, using cheep standard technology we can achieve up to 3 times higher performance than expensive state-of-the-art high performance smart-cameras.
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| 8. |
- Shaber, Mezbah Uddin, et al.
(författare)
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Pipelined DAC architecture using gray coding
- 2005
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Ingår i: Norchip 2005, Proceedings. - : IEEE. - 1424400643 ; , s. 141-144
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Konferensbidrag (refereegranskat)abstract
- This work describes a new architecture suitable for wideband Digital to Analog converter for System-on-Chip. The architecture use switched capacitor pipelined D/A converter design with Selection Inversion based on gray coded bits. A 95dB DC-gain fully differential folded cascode gain-boosted OTA has been designed to be used in each pipelined stage. High linearity up to 61db (SFDR) is achieved for a 5MHz input sign wave at a 50MHz Update frequency. This work describes a new architecture suitable for wideband Digital to Analog converter for System-on-Chip. The architecture use switched capacitor pipelined D/A converter design with Selection Inversion based on gray coded bits. A 95dB DC-gain fully differential folded cascode gain-boosted OTA has been designed to be used in each pipelined stage. High linearity up to 61db (SFDR) is achieved for a 5MHz input sign wave at a 50MHz Update frequency.
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| 9. |
- Shen, Meigen, et al.
(författare)
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UWB radio module design for wireless sensor networks
- 2005
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Ingår i: Norchip 2005, Proceedings. - 1424400643 ; , s. 184-187
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Konferensbidrag (refereegranskat)abstract
- In this paper, we have designed an impulse-based ultra wideband (UWB) radio module for wireless sensor networks (WSN) applications. The UWB radio module includes transceiver block, baseband process unit and power management block. The transceiver block includes Gaussian pulse generator, wideband low noise amplifier (LNA), multiplier, integrator and timing circuits, which use 0.18um, 1P6M CMOS technology. The wideband LNA has a power gain of 10dB and minimum noise figure of 2.7dB. For transceiver block, the power consumption of transmitter is lower than 1mW while the receiver is about 23mW. The liquid-crystal-polymer (LCP)-based System-on-Package (SoP) technology will be used to implement the UWB radio module for low power, low cost and small size.
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| 10. |
- Säll, Erik, 1977-, et al.
(författare)
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Comparison of two thermometer-to-binary decoders for high-performance flash ADCs
- 2005
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Ingår i: Proc. IEEE 23rd NORCHIP Conf., NORCHIP'05. - 1424400643 ; , s. 253-256
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Konferensbidrag (refereegranskat)abstract
- The performance of flash analog-to-digital converters is affected significantly by the choice of thermometer-tobinary decoder topology. In this work two different promising decoder topologies, multiplexer-based and onescounter, are evaluated. Two converters with different decoders, but otherwise similar, are therefore designed. Two test chips are also sent for manufacturing in a 130 nm silicon-on-insulator CMOS technology. The converter performance is evaluated by simulations using foundry provided models. The results show that both decoders can be used in high-speed converters, but the ones-counter decoder is more robust and yield a higher converter efficiency.
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