| 1. |
- Abdulaziz, Mohammed, 1983, et al.
(author)
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Improvement of AM-PM in a 33-GHz CMOS SOI Power Amplifier Using pMOS Neutralization
- 2019
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In: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 29:12, s. 798-801
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Journal article (peer-reviewed)abstract
- This letter presents two highly efficient two-stage power amplifiers (PAs) for 5G applications, implemented in a 22-nm slilicon on insulator (SOI) CMOS technology. High efficiency is achieved by carefully designing the power cells and optimizing the layout. Capacitive neutralization is used to improve the stability and the gain. Both PAs are similar except for the use of nMOS neutralization capacitors in the first one. In the second PA, we propose the use of pMOS capacitors instead to enhance significantly both stability and AM-PM linearity at the same time. For both PAs, the saturated output power is 12.7 dBm andP1 dB is 11.9 dBm from a 0.9-V supply at 33 GHz with a power-added efficiency (PAE) at P1 dB of more than 36%. The PAE at Psat is 38% and 40% for the PA with nMOS and pMOS neutralizations, respectively. The AM-PM up to P3 dB for the PA with nMOS neutralization is 7, and for the one with pMOS neutralization, it is less than 1.3 thanks to the proposed technique.
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| 2. |
- Aljarosha, Alhassan, 1982, et al.
(author)
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A Wideband Contactless and Bondwire-Free MMIC to Waveguide Transition
- 2017
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In: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 27:5, s. 437-439
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Journal article (peer-reviewed)abstract
- A contactless transition from a high-permittivity microstrip line (e_r=9.9) to an air-filled waveguide (WG) has been impedance-matched over a large simulated relative bandwidth of 38% (W-band, 75-110 GHz). The transition couples the EM fields directly from the MMIC's microstrip line via an SIW and an off-chip stub section to a ridge WG section. The novel structure is low loss and suits pick-and-place assembly techniques of mm-Wave MMICs inside metal WGs. The design process is detailed and manufacturing tolerances of the Alumina prototype PCB are discussed. The measured back-to-back structure retains an appreciable insertion loss smaller than 0.8 dB for a single transition and a fractional bandwidth of 28% (72-95~GHz) over which the return loss is greater than 10 dB.
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| 3. |
- An, Sining, 1991, et al.
(author)
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A D-band Dual-Mode Dynamic Frequency Divider in 130nm SiGe Technology
- 2020
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In: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 30:12, s. 1169-1172
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Journal article (peer-reviewed)abstract
- In this work, a dual-mode (divide-by-2 and divide-by-3) dynamic frequency divider is presented. A tunable delay gated ring oscillator (TDGRO) topology is proposed for dual-mode operation and bandwidth extension. It uses a 130 nm gate length SiGe BiCMOS technology with ft and fmax of 250 GHz and 370 GHz, respectively. Verification shows that it works at W-band from 70 GHz to 114 GHz (47.8% bandwidth) for divide-by-2 and works at D-band from 105 GHz to 160 GHz (41.5% bandwidth) for divide-by-3. This divider can be used in integrated phase lock loops (PLLs) at millimeter-wave frequencies.
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| 4. |
- An, Sining, 1991, et al.
(author)
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A Synchronous Baseband Receiver for High-Data-Rate Millimeter-Wave Communication Systems
- 2019
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In: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 29:6, s. 412-414
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Journal article (peer-reviewed)abstract
- A novel synchronous baseband receiver is presented in this letter. With a pilot tone insertion at the transmitter, the proposed baseband receiver can perform carrier recovery (CR) regardless of modulation scheme and/or baud rate. The synchronous baseband receiver has an analog-digital hybrid structure, where a low-cost digital signal processor controls an analog local oscillator (LO) in frequency and phase to achieve CR. This structure requires only one low-cost analog-to-digital converter (ADC) with a sampling rate of 100 MS/s. A proof-of-concept demonstration at E-band achieves 9-Gb/s 64-quadratic-amplitude modulation (QAM) and 16-Gb/s QPSK transmissions.
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| 5. |
- Andersson, Kristoffer, 1976, et al.
(author)
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Resistive SiC-MESFET mixer
- 2002
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In: IEEE Microwave and Wireless Components Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1531-1309 .- 1558-1764. ; 12:4, s. 119-121
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Journal article (peer-reviewed)abstract
- A single-ended silicon carbide resisitve MESFET mixer with minimum conversion loss (CL) of 10.2 dB and an input third order intercept point of 35.7 dB at 3.3 GHz was designed and characterized. A lumped-element, large-signal model was used for modeling the device. The drain-source resistance was measured by taking the real part of the output port impedence. Analysis suggested that the optimum gate bias for minimum CL was -6.7 V.
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| 6. |
- Avolio, G., et al.
(author)
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Small-Versus Large-Signal Extraction of Charge Models of Microwave FETs
- 2014
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In: IEEE Microwave and Wireless Components Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1558-1764 .- 1531-1309. ; 24:6, s. 394-396
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Journal article (peer-reviewed)abstract
- In this letter we extract the parameters of the charge equations of a microwave transistor nonlinear model which is available in commercial CAD tools. In particular, the charge model parameters are extracted starting from small- and large-signal measurements. A better accuracy can be achieved when using large-signal measurements since the model parameters are obtained from experimental data which better reproduce the actual operating condition of the device under test. An advanced 0.15 x 300 mu m(2) pHEMT in GaAs technology, aimed at cold-FET mixer design, is considered as case study.
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| 7. |
- Axelsson, Olle, 1986, et al.
(author)
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Impact of Trapping Effects on the Recovery Time of GaN Based Low Noise
- 2016
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In: IEEE Microwave and Wireless Components Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1558-1764 .- 1531-1309. ; 26:1, s. 31-33
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Journal article (peer-reviewed)abstract
- This study investigates recovery time of the gain of AlGaN/GaN HEMT based low noise amplifiers (LNA) after an input overdrive pulse. Three LNAs, fabricated in two commercial MMIC processes and a Chalmers in-house process, are evaluated. The Chalmers process has an unintentionally doped buffer instead of the intentional Fe doping of the buffer which is standard in commercial GaN HEMT technologies. It is shown that the LNAs from the two commercial processes experience a severe drop in gain after input overdrive pulses higher than 28 dBm, recovering over a duration of around 20 ms. In contrast the LNA fabricated in-house at Chalmers experienced no visible effects up to an input power of 33 dBm. These results have impact for radar and electronic warfare receivers, which need to be operational immediately after an overdrive pulse. The long time constants suggest that these effects are due to trapping in the transistors with the Fe doped buffer playing an important role.
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| 8. |
- Banik, Biddut Kumar, 1978, et al.
(author)
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Millimeter Wave Characterization of a Catadioptric Lens for Imaging Applications
- 2009
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In: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 19:11, s. 680-682
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Journal article (peer-reviewed)abstract
- Characterization of a catadioptric dielectric lens-horn configuration for short-range sensing and imaging is presented. The focusing property is investigated both numerically and experimentally at 108 GHz. The lens-horn provides a focal spot of ~ 0.9λ at a distance of ~ 4.5λ. An imaging example employing the lens in a CW imaging setup is presented. A test pattern was imaged and a marked improvement in image resolution was observed. With the aid of the lens, features close to the wavelength are resolved, which are absent or indistinguishable otherwise.
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| 9. |
- Bao, M. Q., et al.
(author)
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A D-Band Frequency Sixtupler MMIC With Very Low DC Power Consumption
- 2016
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In: IEEE Microwave and Wireless Components Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1558-1764 .- 1531-1309. ; 26:9, s. 726-728
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Journal article (peer-reviewed)abstract
- A novel frequency sixtupler is proposed and verified experimentally. It consists of an even-order harmonics generating stage and a mixing stage to convert the 2nd and the 4th harmonics into the 6th harmonic. Transistors in those two stages operate in class-C condition, thus, the sixtupler consumes very low DC power. A proof-of-concept circuit is designed and manufactured in a 0.25 mu m InP DHBT Technology. The sixtupler delivers a maximum output power of -3.5 dBm at 121 GHz at an input power of 7 dBm. Its 3-dB bandwidth of the output power is 25 GHz in the frequency range from 100 GHz to 125 GHz. It demonstrates also more than 10 dBc rejection ratio of the unwanted harmonics in the frequency range from 110 to 125 GHz. The sixtupler consumes a DC power of only 20 mW, which to the authors knowledge, is the lowest among sixtuplers published so far. The sixtupler also achieves a state-of-the-art peak power efficiency of 1.9%.
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| 10. |
- Bao, M. Q., et al.
(author)
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A D-Band Keyable High Efficiency Frequency Quadrupler
- 2014
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In: IEEE Microwave and Wireless Components Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1558-1764 .- 1531-1309. ; 24:11, s. 793-795
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Journal article (peer-reviewed)abstract
- A D-band frequency quadrupler consisting of two cascaded push-push doublers is designed and manufactured in a 0.25 mu m InP DHBT technology. Each doubler has a Marchand balun implemented by broadside-coupled transmission lines, folded in a rectangular shape. The second balun, operating at a half of output frequency, is located inside of the first one for minimizing the chip size. The frequency quadrupler with a dc power consumption of 47 mW has a maximum conversion gain of 2 dB, and exhibits 12 to 25 dBc rejection ratio of the undesired first to fifth harmonics in the frequency range from 110 to 130 GHz. The quadrupler demonstrates a power efficiency of 10%, which is the highest among published quadruplers, as well as the highest conversion gain and an output power of 5 similar to 7 dBm without using power amplifiers. The chip size is 0.77 mm(2). By switching a cascode transistor, the quadrupler can also be used as an on-off keying modulator.
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