| 1. |
- Abbas, Muhammad, et al.
(författare)
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On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 60:4, s. 926-937
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, the fixed-point implementation of adjustable fractional-delay filters using the Farrow structure is considered. Based on the observation that the sub-filters approximate differentiators, closed-form expressions for the L-2-norm scaling values at the outputs of each sub-filter as well as at the inputs of each delay multiplier are derived. The scaling values can then be used to derive suitable word lengths by also considering the round-off noise analysis and optimization. Different approaches are proposed to derive suitable word lengths including one based on integer linear programming, which always gives an optimal allocation. Finally, a new approach for multiplierless implementation of the sub-filters in the Farrow structure is suggested. This is shown to reduce register complexity and, for most word lengths, require less number of adders and subtracters when compared to existing approaches.
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| 2. |
- Abdulaziz, Mohammed, et al.
(författare)
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Improving Receiver Close-In Blocker Tolerance by Baseband Gm-C Notch Filtering
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328. ; 66:3, s. 885-896
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS technology. Since close-in blockers are challenging to reject at RF, the receiver features a baseband (BB) notch filter, which effectively sinks close-in blocker current directly from the output of an LNTA and passive mixer structure. The notch-filter frequency can be tuned to match the blocker offset frequency, and the measurements indicate a significant improvement in the overall front-end interference robustness, while sensitivity remains unaffected. To optimize notch performance, the BB impedance is analyzed in detail. The front-end RF range is 750 MHz-3 GHz with an RF channel bandwidth of 20 MHz corresponding to 10-MHz BB bandwidth. The notch frequency is programmable from 16, which is less than one octave from the channel edge, up to 160 MHz. The gain-compression improvement is upto 9 dB, while IIP2 can be increased by more than 26 dB without calibration and IIP3 is 1 dBm. The current overhead for the notch function is between 7.5 and 30 mA, but it only exists under strong blocker conditions as the notch filter can be switched off if strong blockers are absent. The total front-end current consumption excluding the notch filter varies with LO frequency from 31 to 44 mA from a 1.2-V supply.
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| 3. |
- Alty, S. R., et al.
(författare)
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Efficient time-recursive implementation of matched filterbank spectral estimators
- 2005
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - 1057-7122 .- 1558-1268. ; 52:3, s. 516-521
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a computationally efficient sliding window time updating of the Capon and amplitude and phase,estimation (APES) matched filterbank spectral estimators based on the time-variant displacement structure of the data covariance matrix. The presented algorithm forms a natural extension of the most computationally efficient algorithm to date, and offers a significant computational gain as compared to the computational complexity associated with the batch re-evaluation of the spectral estimates for each time-update. Furthermore, via simulations, the algorithm is found to be numerically superior to the time-updated spectral estimate formed from directly updating the data covariance matrix.
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| 4. |
- Andersson, Ola, et al.
(författare)
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Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters
- 2005
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - Piscataway : IEEE. - 1549-8328. ; 52:11, s. 2265-2275
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Tidskriftsartikel (refereegranskat)abstract
- The current-steering digital-to-analog converter (DAC) is the most common type of DAC for high-speed applications. Glitches present in the DAC output contribute to nonlinear distortion in the DAC transfer characteristics degrading the circuit performance. One source of glitches is asymmetry in the settling behavior when switching on and off a current source. A behavioral-level model of this nonideal behavior is derived in this work. Further, a method with low computational complexity for estimating the influence of the modeled errors in the frequency domain is developed. This method can be utilized by circuit designers to derive circuit requirements for fulfilling a given frequency-domain specification, potentially relaxing the requirements compared with a worst-case analysis. Examples of model utilization are given in terms of an analytical examination and MATLAB simulations. A good agreement between simulated and analytical results is obtained.
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| 5. |
- Andersson, Oskar, et al.
(författare)
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Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
- 2016
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Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 63:6, s. 806-817
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Tidskriftsartikel (refereegranskat)abstract
- In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch architecture designs, and process options. Furthermore, deployment of multiple threshold voltages (Vth) options in a single standard-cell/bitcell enables additional architectural choices. Silicon measurements from five memory designs, optimized at the transistor level in conjunction with gate-level optimizations, are considered to demonstrate the different trade-off corners. Measurements show that substituting the storage element in an SCM with a D-latch using transistor stacking and channel length stretching results in lowest leakage power. Alternatively, a pass- transistor based latch as storage element reduces the area footprint at a cost of reduced access speed, which can be compensated by using a lower-Vth pass-transistor. However, relatively high speed (tens of MHz) in the near- to subthreshold (sub-Vth) region is achievable if general purpose transistors are used instead of low power transistors. A discussion is included to illustrate when to implement ULV memories using SCMs and when to choose sub-Vth SRAMs. The discussion shows that the border is between 4-6 kb, depending on the number of words and the wordlength configuration.
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| 6. |
- Andersson, Rikard, et al.
(författare)
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Using Rotator Transformations to Simplify FFT Hardware Architectures
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 67:12, s. 4784-4793
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%.
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| 7. |
- Andreani, Pietro
(författare)
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A time-variant analysis of the 1/f2 phase noise in CMOS parallel LC-tank quadrature oscillators
- 2006
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Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 53:8, s. 1749-1760
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a study of 1/f/sup 2/ phase noise in quadrature oscillators built by connecting two differential LC-tank oscillators in a parallel fashion. The analysis clearly demonstrates the necessity of adopting a time-variant theory of phase noise, where a more simplistic, time-invariant approach fails to explain numerical simulation results even at the qualitative level. Two topologies of 5-GHz parallel quadrature oscillators are considered, and compact but nevertheless highly general, closed-form formulas are derived for the phase noise caused by the losses in the LC-tanks and by the noisy currents in the MOS transistors. A large number of spectreRF simulations, covering a wide range of working conditions for the oscillators, is used to validate the theoretical analysis.
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| 8. |
- Attari, Mohammad, et al.
(författare)
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An Application Specific Vector Processor for Efficient Massive MIMO Processing
- 2022
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328. ; , s. 1-12
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22FD-SOI technology running at a clock frequency of 800 . The system achieves a maximum detection throughput of 0.75 Gb/s/mm $^2$ for a $128\times 8$ massive MIMO system.
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| 9. |
- Bevilacqua, Andrea, et al.
(författare)
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An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 59:5, s. 938-945
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Tidskriftsartikel (refereegranskat)abstract
- We present a study of tail-bias-current 1/f noise upconversion into 1/f(3) phase noise for both CMOS Colpitts and differential-pair LC oscillators. We focus on the incremental Groszkowski effect, i.e., the modulation of the shift in oscillation frequency induced by the higher current harmonics flowing into the LC tank of a harmonic oscillator induced by bias instabilities, as we show that there is no upconversion of 1/f noise into phase noise from the core MOS transistors in either topologies. Quantitative results match very well numerical simulations run with spectreRF, and show that the Groszkowski effect may indeed be a dominant cause of 1/f(3) phase noise generation.
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| 10. |
- Bruni, Giovanni, 1989, et al.
(författare)
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DPTC - An FPGA-Based Trace Compression
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 67:1, s. 189-197
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Tidskriftsartikel (refereegranskat)abstract
- Recording of flash-ADC traces is challenging from both the transmission bandwidth and storage cost perspectives. This work presents a configuration-free lossless compression algorithm, which addresses both limitations, by compressing the data on-the-fly in the controlling FPGA. Thus it can easily be used directly in front-end electronics. The method first computes the differences between consecutive samples in the traces, thereby concentrating the most probable values around zero. The values are then stored as groups of four, with only the necessary least-significant bits in a variable-length code, packed in a stream of 32-bit words. To evaluate the efficiency, the storage cost of compressed traces is modeled as a baseline cost including ADC noise, and a cost for pulses that depends on amplitude and width. The free parameters and the validity of the model are determined by compressing artificial traces with varying characteristics. The compression method was also applied to actual data from different types of detectors. A typical storage cost is around 4 to 5 bits per sample. Code for the FPGA implementation in VHDL and for the CPU decompression routine in C are available as open source software, both able to operate at speeds of 400 Msamples/s.
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