| 1. |
- Strak, Adam, et al.
(författare)
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Power-supply and substrate noise-induced timing jitter in nonoverlapping clock generation circuits
- 2008
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Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268 .- 1549-8328 .- 1558-0806. ; 55:4, s. 1041-1054
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Tidskriftsartikel (refereegranskat)abstract
- This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mu m CMOS process parameters, and a reference simulation in 0.18 mu m is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mu m process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.
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| 2. |
- Abbas, Muhammad, et al.
(författare)
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On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 60:4, s. 926-937
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, the fixed-point implementation of adjustable fractional-delay filters using the Farrow structure is considered. Based on the observation that the sub-filters approximate differentiators, closed-form expressions for the L-2-norm scaling values at the outputs of each sub-filter as well as at the inputs of each delay multiplier are derived. The scaling values can then be used to derive suitable word lengths by also considering the round-off noise analysis and optimization. Different approaches are proposed to derive suitable word lengths including one based on integer linear programming, which always gives an optimal allocation. Finally, a new approach for multiplierless implementation of the sub-filters in the Farrow structure is suggested. This is shown to reduce register complexity and, for most word lengths, require less number of adders and subtracters when compared to existing approaches.
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| 3. |
- Andersson, Rikard, et al.
(författare)
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Using Rotator Transformations to Simplify FFT Hardware Architectures
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 67:12, s. 4784-4793
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%.
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| 4. |
- Bruni, Giovanni, 1989, et al.
(författare)
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DPTC - An FPGA-Based Trace Compression
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 67:1, s. 189-197
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Tidskriftsartikel (refereegranskat)abstract
- Recording of flash-ADC traces is challenging from both the transmission bandwidth and storage cost perspectives. This work presents a configuration-free lossless compression algorithm, which addresses both limitations, by compressing the data on-the-fly in the controlling FPGA. Thus it can easily be used directly in front-end electronics. The method first computes the differences between consecutive samples in the traces, thereby concentrating the most probable values around zero. The values are then stored as groups of four, with only the necessary least-significant bits in a variable-length code, packed in a stream of 32-bit words. To evaluate the efficiency, the storage cost of compressed traces is modeled as a baseline cost including ADC noise, and a cost for pulses that depends on amplitude and width. The free parameters and the validity of the model are determined by compressing artificial traces with varying characteristics. The compression method was also applied to actual data from different types of detectors. A typical storage cost is around 4 to 5 bits per sample. Code for the FPGA implementation in VHDL and for the CPU decompression routine in C are available as open source software, both able to operate at speeds of 400 Msamples/s.
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| 5. |
- Buonomo, Antonio, et al.
(författare)
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A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 60:12, s. 3126-3135
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Tidskriftsartikel (refereegranskat)abstract
- This paper proposes a simple and effective modification of the conventional divide-by-two injection locked frequency divider (ILFD) with direct-injection aimed at allowing both the divide-by-two and the divide-by-three modes of operation. The proposed circuit does not employ additional inductors as usual in divide-by-three ILFDs, but exploits the combined effect of two independent injection techniques. The resulting locking range for the divide-by-three mode is comparable in size to that for the divide-by-two. Thus, the proposed circuit can be an optimum alternative to existing dividers, due to the flexibility of two division ratios and due to the absence of additional inductors. An intuitive explanation of the locking mechanism underlying this ILFD and a quantitative analysis are provided, allowing one to predict the amplitude and phase of oscillation in the locked mode, as well as the locking range, with approximate closed-form expressions. Measurements on a circuit prototype and results from SPICE simulations demonstrate the effectiveness of the circuit and validate the theoretical model and the resulting formulas.
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| 6. |
- Chen, H., et al.
(författare)
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Huicore : A Generalized Hardware Accelerator for Complicated Functions
- 2022
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 69:6, s. 2463-2476
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Tidskriftsartikel (refereegranskat)abstract
- Emerging advanced System-on-Chip (SoC) designs contain more and more complicated functions to be accelerated. This presents a challenge to conventional design approaches which use different hardware architectures or separate hardware accelerators to implement the various functions. To tackle this challenge, for the first time, we propose a generalized hardware accelerator called 'Huicore' to speed up diverse functions on the same substrate. Through the analysis and transformation of mathematical characteristics, we reveal the commonality of many complicated functions using the CORDIC algorithm. Then we explore a reconfigurable architecture to implement them. The proposed reconfigurable accelerator can not only accelerate the implementation of many complicated functions, but also has small area, low power consumption and high precision. It is very suitable for integration in a SoC system to accelerate the implementation of various applications.
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| 7. |
- Chen, Hui, et al.
(författare)
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Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 68:8, s. 3293-3304
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Tidskriftsartikel (refereegranskat)abstract
- This paper proposes a low-complexity method and architecture to compute the logarithm of complex numbers based on coordinate rotation digital computer (CORDIC). Our method takes advantage of the vector mode of circular CORDIC and hyperbolic CORDIC, which only needs shift-add operations in its hardware implementation. Our architecture has lower design complexity and higher performance compared with conventional architectures. Through software simulation, we show that this method can achieve high precision for logarithm computation, reaching the relative error of 10(-7). Finally, we design and implement an example circuit under TSMC 28nm CMOS technology. According to the synthesis report, our architecture has smaller area, lower power consumption, higher precision and wider operation range compared with the alternative architectures.
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| 8. |
- Chen, Hui, et al.
(författare)
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Symmetric-Mapping LUT-Based Method and Architecture for Computing X-Y-Like Functions
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 68:3, s. 1231-1244
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Tidskriftsartikel (refereegranskat)abstract
- We propose a new method and hardware architecture to compute the functions expressed as XY ( X and Y are arbitrary floating-point numbers), which can support arbitrary Nth root, exponential and power operations. Because of the complexity of direct computation, we usually convert it to logarithm, multiplication, and antilogarithm operations. Traditional approaches suffer from long latency, large area and high power consumption. To solve this problem, we propose a symmetric-mapping lookup table (SM-LUT) to be capable of computing log(2) x (x is an element of [1, 2]) and 2 x (x is an element of [0, 1]) simultaneously. It lays the foundation for computing XY. To further improve hardware performance of our architecture, we propose a multi-region address searcher to speed up the calculation of SM-LUT. In addition, we use an optimized Vedic multiplier to shorten the critical path and improve the efficiency of multiplication, which is included in computing X-Y. Under the TSMC 40nm CMOS technology, we design and synthesize a reference circuit to compute X-Y with a maximum relative error of 10(-3). The report shows that the reference circuit achieves the area of 14338.50 mu m(2) and the power consumption of 4.59 mW at the frequency of 1 GHz. In comparison with the state-of-the-art work under the same input range and similar precision, it saves 78.57% area and 80.42% power consumption for (N)root R computation and 82.89% area and 81.89% power consumption for R-N computation averagely. On top of that, our architecture reduces the computation latency by 62.77% averagely and has one more order of magnitude of energy efficiency than others.
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| 9. |
- Chen, J., et al.
(författare)
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Distributed Control of Multi-Functional Grid-Tied Inverters for Power Quality Improvement
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers Inc.. - 1549-8328 .- 1558-0806. ; 68:2, s. 918-928
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Tidskriftsartikel (refereegranskat)abstract
- Multi-functional grid-tied inverters (MFGTIs) have been investigated recently for improving the power quality (PQ) of microgrids (MGs) by exploiting the residual capacity (RC) of distributed generators. Several centralized and decentralized methods have been proposed to coordinate the MFGTIs. However, with the increasing number of the MFGTIs, it demands a method with improved reliability and flexibility, which are characteristics of distributed framework that has not been introduced into the PQ improvement (PQI) field before. In this paper, we propose a distributed consensus method to undertake the PQI task. The task is proportionally shared among the MFGTIs according to their instant RCs. Besides, most of the existing methods assume that the RCs of the MFGTIs are sufficient for tackling the PQ problem (PQP), which is not always true. In the case of insufficient RC, the active power output of each MFGTI is scaled down by the same factor determined by a proposed leader-follower protocol to make room for the task. In summary, the PQP is dealt with in both cases of sufficient and insufficient RC under the distributed control framework. Finally, simulations and hardware-in-the-loop experiments of an MG consisting of three 10kVA MFGTIs are presented to verify the effectiveness of the proposed methods. © 2004-2012 IEEE.
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| 10. |
- Chen, Sau-Gee, et al.
(författare)
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Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:10, s. 2869-2877
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
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