| 1. |
- Agelis, Sacki, et al.
(författare)
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System-Level Runtime Reconfigurablity - Optical Interconnection Networks for Switching Applications
- 2004
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Ingår i: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. - Athens, USA : CSREA Press. - 1932415424 - 9781932415421 ; , s. 155-162
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Konferensbidrag (refereegranskat)abstract
- The performance requirements on data and telecommunication switches and routers are continuously increasing and it is evident that new ideas and architectures must come to light to satisfy these new demands. In this paper, a runtime reconfigurable modular design approach is presented, using state-of-the-art microoptical-electrical mechanical system (MOEMS) components. The paper introduces a novel field of reconfigurability, where reconfiguration is made on the system level instead of, e.g. fine-granularity reconfigurable logic. Different reconfigurable system solutions with support to adapt for asymmetric traffic patterns are proposed and compared to see how design choices affect flexibility, performance etc. The proposed solutions are characterized by their multistage networks with reconfigurable shuffle patterns.
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| 2. |
- Andersson, Per, et al.
(författare)
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Automatic local memory architecture generation for data reuse in custom data paths
- 2004
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Ingår i: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. - 1932415424 ; , s. 137-144
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Konferensbidrag (refereegranskat)abstract
- Traditional high level synthesis is able to yield high computational resource utilisation and short critical paths. The shortcomings of the generated designs usually lies in the memory architecture. To achieve good performance on a FPGA, the data must reside in the fast on-chip memories, but these are commonly too small for the data being processed. Traditional high level synthesis cannot cope with this situation. In this paper we present a technique for automatic generation of a memory architecture, data paths and associated controllers from a high level language such as C. Data reused during the processing are stored in a local memory, resulting in high performance even when the data are stored in shared off-chip memory. The technique is based on data dependence and data access pattern analysis. Commonly used data are duplicated in on-chip memory. High memory efficiency is achieved by rearranging the data memory layout during copying. We have applied our technique to typical signal analysis tasks. The results show that the data path does not need to stall waiting for data, even when all data are stored in a shared off-chip memory. The experiments have been carried ont on a Xilinx Virtex2 FPGA.
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| 3. |
- Johnsson, Dennis, et al.
(författare)
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Two-level Reconfigurable Architecture for High-Performance Signal Processing
- 2004
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Ingår i: ERSA'04, The 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms. - Arthens : CSREA Press. - 9781932415421 ; , s. 177-183
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Konferensbidrag (refereegranskat)abstract
- High speed signal processing is often performed as a pipeline of functions on streams or blocks of data. In order to obtain both flexibility and performance, parallel, reconfigurable array structures are suitable for such processing. The array topology can be used both on the micro and macro-levels, i.e. both when mapping a function on a fine-grained array structure and when mapping a set of functions on different nodes in a coarse-grained array. We outline an architecture on the macro-level as well as explore the use of an existing, commercial, word level reconfigurable architecture on the micro-level. We implement an FFT algorithm in order to determine how much of the available resources are needed for controlling the computations. Having no program memory and instruction sequencing available, a large fraction, 70%, of the used resources is used for controlling the computations, but this is still more efficient than having statically dedicated resources for control. Data can stream through the array at maximum I/O rate, while computing FFTs. The paper also shows how pipelining of the FFT algorithm over a two-level reconfigurable array of arrays can be done in various ways, depending on the application demands.
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