| 1. |
- Fakih, Maher, et al.
(författare)
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Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems
- 2019
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Ingår i: Journal of Low Power Electronics and Applications. - : MDPI AG. - 2079-9268. ; 9:1
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Tidskriftsartikel (refereegranskat)abstract
- With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
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| 2. |
- Andersson, Henrik, Dr, 1975-, et al.
(författare)
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PEDOT : PSS thermoelectric generators printed on paper substrates
- 2019
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Ingår i: Journal of Low Power Electronics and Applications. - : MDPI AG. - 2079-9268. ; 9:2
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Tidskriftsartikel (refereegranskat)abstract
- Flexible electronics is a field gathering a growing interest among researchers and companies with widely varying applications, such as organic light emitting diodes, transistors as well as many different sensors. If the circuit should be portable or off-grid, the power sources available are batteries, supercapacitors or some type of power generator. Thermoelectric generators produce electrical energy by the diffusion of charge carriers in response to heat flux caused by a temperature gradient between junctions of dissimilar materials. As wearables, flexible electronics and intelligent packaging applications increase, there is a need for low-cost, recyclable and printable power sources. For such applications, printed thermoelectric generators (TEGs) are an interesting power source, which can also be combined with printable energy storage, such as supercapacitors. Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate), or PEDOT:PSS, is a conductive polymer that has gathered interest as a thermoelectric material. Plastic substrates are commonly used for printed electronics, but an interesting and emerging alternative is to use paper. In this article, a printed thermoelectric generator consisting of PEDOT:PSS and silver inks was printed on two common types of paper substrates, which could be used to power electronic circuits on paper.
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| 3. |
- Bharadwaj, Bharadwaj, et al.
(författare)
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Adaptative Techniques to Reduce Power in Digital Circuits
- 2011
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Ingår i: Journal of Low Power Electronics and Applications. - : MDPI AG. - 2079-9268. ; 1:2, s. 261-276
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Tidskriftsartikel (refereegranskat)abstract
- CMOS chips are engineered with sufficient performance margins to ensure that they meet the target performance under worst case operating conditions. Consequently, excess power is consumed for most cases when the operating conditions are more benign. This article will review a suite of dynamic power minimization techniques, which have been recently developed to reduce power consumption based on actual operating conditions. We will discuss commonly used techniques like Dynamic Power Switching (DPS), Dynamic Voltage and Frequency Scaling (DVS and DVFS) and Adaptive Voltage Scaling (AVS). Recent efforts to extend these to cover threshold voltage adaptation via Dynamic Voltage and Threshold Scaling (DVTS) will also be presented. Computation rate is also adapted to actual work load requirements via dynamically changing the hardware parallelism or by controlling the number of operations performed. These will be explained with some examples from the application domains of media and wireless signal processing.
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| 4. |
- Dwivedi, Satyam, et al.
(författare)
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Power scalable radio receiver design based on signal and interference condition
- 2012
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Ingår i: Journal of Low Power Electronics and Applications. - : MDPI AG. - 2079-9268. ; 2:4, s. 242-264
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Tidskriftsartikel (refereegranskat)abstract
- A low power adaptive digital baseband architecture is presented for a low-IF receiver of IEEE 802.15.4-2006. The digital section's sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle the worst case conditions. We show that in a 0.13 μm CMOS technology, for an adaptive digital baseband section of the receiver, power saving can be up to 85% (0.49mW against 3.3mW) in favorable interference and signal conditions. The proposed concepts in the design are tested using a receiver test setup where the design is hosted on a FPGA.
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