| 1. |
- Al-Obaidi, Mohammed, et al.
(författare)
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Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
- 2013
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Ingår i: 2013 IEEE International Symposium on Circuits and Systems (ISCAS). - 2158-1525 .- 0271-4310. - 9781467357609 - 9781467357623 ; , s. 293-296
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Konferensbidrag (refereegranskat)abstract
- In LTE base-stations, RoHC is a processingintensive algorithm that may limit the system from serving a large number of users when it is used to compress the VoIP packets of mobile traffic. In this paper, a hardware-software and a full-hardware solution are proposed to accelerate the RoHC compression algorithm in LTE base-stations and enhance the system throughput and capacity. Results for both solutions are discussed and compared with respect to design metrics like throughput, capacity, power consumption, and hardware resources. This comparison is instrumental in taking architectural level trade-off decisions in-order to meet the present day requirements and also be ready to support a future evolution. In terms of throughput, a gain of 20% (6250 packets/sec) is achieved in the HW-SW implementation by accelerating the Cyclic Redundancy Check (CRC) and the Least Significant Bit (LSB) encoding in hardware. The full-HW implementation leads to a throughput of 45 times (244000 packets/sec) compared to the SW-Only implementation. The full-HW solution consumes more Adaptive Look-Up Tables (7477 ALUTs) compared to the HW-SW solution (2614 ALUTs) when synthesized on Altera’s Arria II GX FPGA.
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| 2. |
- Berkeman, Anders, et al.
(författare)
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A configurable divider using digit recurrence
- 2003
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Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - 2158-1525 .- 0271-4310. ; 5, s. 333-336
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Konferensbidrag (refereegranskat)abstract
- The division operation is essential in many digital signal processing algorithms. For a hardware implementation, the requirements and constraints on the divider circuit differ significantly with different applications. Therefore, it is not possible to design one divider component having optimal performance and cost for all target applications. Instead, the presented divider has a modular architecture, based on instantiation of small efficient divider sub-blocks. The configuration of the divider architecture is set by a number of parameters controlling wordlength, number of quotient bits, number of clock cycles per operation, and fixed or floating point operation. Digit recurrence algorithms with carry save arithmetic and on-the-fly two's complement output quotient conversion are used to make the sub-blocks small, fast and power efficient, The modularity gives the designer freedom to elaborate different parameters to explore the design space. Two applications using the proposed divider are presented. Furthermore, an example divider circuit has been fabricated and performance measurements are included.
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| 3. |
- Chen, Cheng, et al.
(författare)
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A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS
- 2007
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Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - 0271-4310 .- 2158-1525. ; , s. 1709-1712
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Konferensbidrag (refereegranskat)abstract
- A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm2. © 2007 IEEE.
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| 4. |
- Durkalec, Laurent, et al.
(författare)
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Properties of RF bandpass amplifier topology with Q-enhancing
- 2002
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Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - 0271-4310 .- 2158-1525. ; 1, s. 529-532
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Konferensbidrag (refereegranskat)abstract
- This paper describes a bandpass amplifier topology for the GHz range using Q-enhancing that allows a systematic design approach to be used to control linearity, noise and power consumption. Frequency selectivity is achieved by a negative feedback network using a LC tank and a positive feedback networks using a resistor to achieve Q-enhancing. The feedback networks are fully passive in order to minimize noise and distortion.
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| 5. |
- Hedberg, Hugo, et al.
(författare)
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Implementation of a labeling algorithm based on contour tracing with feature extraction
- 2007
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Ingår i: [Host publication title missing]. - 2158-1525 .- 0271-4310. ; , s. 1101-1104
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Konferensbidrag (refereegranskat)abstract
- This paper describes an architecture of a connected-cluster labeling algorithm for binary images based on contour tracing with feature extraction. The implementation is intended as a hardware accelerator in a self contained real-time digital surveillance system. The algorithm has lower memory requirements compared to other labeling techniques and can guarantee labeling of a predefined number of clusters independent of their shape. In addition, features especially important in this particular application are extracted during the contour tracing with little increase in hardware complexity. The implementation is verified on an FPGA in an embedded system environment with an image resolution of 320 × 240 at a frame rate of 25 fps. The implementation supports labeling of 61 independent clusters, extracting their location, size and center of gravity. © 2007 IEEE.
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| 6. |
- Jiang, Hongtu, et al.
(författare)
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FPGA implementation of controller-datapath pair in custom image processor design
- 2004
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Ingår i: Proceedings of the 2004 International Symposium on Circuits and Systems. - 2158-1525 .- 0271-4310. ; 5, s. 141-144
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Konferensbidrag (refereegranskat)abstract
- In order to reduce the effort of the controller design in the customized image convolution processor, a controller synthesis tool is developed based on [9] to support the design flow from a system or algorithm specification to RTL level VHDL. Architecture extensions to basic FSMs structures are implemented with the purpose of optimizing controller design for area and power consumption. Together with controller implementation, a custom datapath architecture with three level memory hierarchies is developed aiming at a real-time power efficient image processing solution with low I/O bandwidth requirements. The complete design is prototyped on Xilinx Virtex 2 platform with comparable performance with that of TI C64x processor at only 2/15 of its clock frequency.
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| 7. |
- Kristensen, Fredrik, et al.
(författare)
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Real-time extraction of maximally stable extremal regions on an FPGA
- 2007
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Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - 2158-1525 .- 0271-4310. ; , s. 165-168
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Konferensbidrag (refereegranskat)abstract
- This paper describes the implementation of a real-time Maximally Stable Extremal Region (MSER) detector. In order to reach real-time performance, both algorithmic and memory issues have been addressed. The Union-find algorithm, which is the heart of the MSER detector, is extended to create linked regions that significantly decrease the time to extract MSERs. Hash indexed memory structures are used to locate stored regions fast while keeping the amount of stored data low. The design is verified by including it in a demonstrator circuit. Timing and memory requirements are presented for the demonstrator and as a function of image resolution. © 2007 IEEE.
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| 8. |
- Lenart, Thomas, et al.
(författare)
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A 2048 complex point FFT processor using a novel data scaling approach
- 2003
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Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - 2158-1525 .- 0271-4310. ; 4, s. 45-48
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Konferensbidrag (refereegranskat)abstract
- In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the FFT processor can operate on a wide range of input signals without performance loss. Compared to existing block scaling methods, like implementations of Convergent Block Floating Point (CBFP), the memory requirements can be reduced while preserving the SNR. The FFT processor has been synthesized and sent for fabrication in a 0.35μm standard CMOS technology. In netlist simulations, the FFT processor is capable of calculating a 2048 complex point FFT or IFFT in 27μs with a maximum clock frequency of 76MHz.
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| 9. |
- Liu, Liang, et al.
(författare)
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A unified multi-mode MIMO detector with soft-output
- 2012
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Ingår i: [Host publication title missing]. - 2158-1525 .- 0271-4310.
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Konferensbidrag (refereegranskat)abstract
- This paper presents an area/energy efficient soft-output MIMO detector that supports the detection of spatial-multiplexing (SM), spatial-diversity (SD), and space-division-multiple-access (SDMA)signals. The developed near-optimal detection algorithms for these tree modes share most of the mathematical operations to enable extensive hardware reuse. A unified VLSI architecture is accordingly designed to be reconfigured to different modes. The detector was implemented using a 65-nm CMOS technology with 0.25 mm2 core area, representing a 70% hardware-resource saving to state-of-the-art detectors. Operating at 167-MHz clock frequency with 1.2-V supply, the detector achieves 1 Gb/s peak throughput and only consumes 59.3 pJ/b energy.
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| 10. |
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