| 1. |
- Ahsan, Naveed, 1974-, et al.
(författare)
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Applications of Programmable Microwave Function Array (PROMFA)
- 2007
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Ingår i: Proceedings of the IEEE European Conference on Circuit Theory and Design (ECCTD 2007), August 26-30, 2007, Seville, Spain. - : IEEE. - 9781424413416 ; , s. 164 -167
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Konferensbidrag (refereegranskat)abstract
- This paper describes the use of programmable microwave function array (PROMFA) for different microwave application. The PROMFA concept is based on an array of generic cells, in which a number of different functions can be realized. Each PROMFA cell is a four-port circuit, that can either be programmed independently or collectively according to a specific need. Specifically, the phase shift capability in a single PROMFA cell, useful for a new type of phase shifter design is discussed. The paper also presents the functionality of this new architecture as a beamforming network. As an example case an active corporate feed network and a tunable recursive filter is demonstrated. Simulated and measured results are presented.
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| 2. |
- Backenius, Erik, et al.
(författare)
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Reduction of simultaneous switching noise in analog signal band
- 2007
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Ingår i: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07. - 9781424413416 ; , s. 148-151
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Konferensbidrag (refereegranskat)abstract
- In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.
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| 3. |
- Eghbali, Amir, et al.
(författare)
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An arbitrary bandwidth transmultiplexer and its application to flexible frequency-band reallocation networks
- 2007
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Ingår i: Proc. European Conf. Circuit Theory Design, Seville, Spain, Aug. 26-30, 2007. - : IEEE. - 9781424413416 - 9781424413423 ; , s. 248-251
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Konferensbidrag (refereegranskat)abstract
- In this paper, we introduce a non-uniform transmultiplexer capable of generating arbitrary-bandwidth user signals. The transmultiplexer consists of linear-phase finite-length impulse response (FIR) filters and Farrow structures for arbitrary-rate interpolation/decimation. By applying the FIR rational sampling rate conversion (SRC) equivalent of the Farrow structure, we model the behavior of the multiplexer and derive the conditions under which the system can approximate perfect reconstruction. Futhermore, we illustrate the functionality of the proposed transmultiplexer and we analyze the performance and functionality of a flexible frequency-band reallocation (FFBR) network using this transmultiplexer.
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| 4. |
- Rodríguez de Llera González, Delia, et al.
(författare)
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EDA for RF and analog front-ends in the 4G era : Challenges and solutions
- 2007
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Ingår i: European Conference on Circuit Theory and Design 2007, ECCTD 2007. - 9781424413416 ; , s. 24-27
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Konferensbidrag (refereegranskat)abstract
- Convergence into 4G wireless communication systems pushes the design of radio receivers beyond limits unconceivable only few years ago. The complexity of RF systems has increased enormously as new communication standards have appeared in the wireless scenario. The convergence trends, enabled by the advances in fabrication technology, have driven the Software Defined Radio (SDR) more and more into the RF and analog front-end. There is a clear need for design automation and advanced simulation techniques at the different levels that go from the system idea to chip fabrication. Reducing the number of design iterations between these levels is key in meeting the increasingly tight time-to-market constraints. As of today, there is not a single tool that covers the complete design flow. Instead, there is an intricate puzzle of design and simulation tools that focus on the various steps that go from system to silicon. The amount of RF and analog EDA tools available is certainly scarce in comparison with their digital counterparts. Most of the design work still depends on the radio engineer, making the process less than optimal. This paper describes some of the challenges faced by today's radio designers and discusses some of the solutions provided by the EDA community.
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| 5. |
- Rusu, Ana, et al.
(författare)
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Flexible ADCs for wireless mobile radios
- 2007
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Ingår i: 18th European Conference on Circuit Theory Design, ECCTD 2007. - 9781424413416 ; , s. 172-175
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Konferensbidrag (refereegranskat)abstract
- The evolution of wireless mobile devices calls for "all-in-one-device", which support a large number of wireless standards and allows wireless connectivity and roaming. This creates the need for adaptive circuits that are able to reconfigure themselves to trade-off power dissipation for performance, depending on the wireless standard to be supported and the required Quality of Service. Therefore, the key features of such mobile devices are flexibility and adaptability. This paper presents the ADCs suitable for mobile radios, keeping focus on flexible architectures. Finally, a programmable ADCs array, which can digitize signal bands from cellular to UWB is presented.
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| 6. |
- Säll, Erik, 1977-, et al.
(författare)
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Thermometer-to-binary decoders for flash analog-to-digital converters
- 2007
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Ingår i: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07. - 9781424413416 ; , s. 240-243
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Konferensbidrag (refereegranskat)abstract
- Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.
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| 7. |
- Yun, Ruida, et al.
(författare)
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LMS-based calibration of pipelined ADCs including linear and nonlinear errors
- 2007
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Ingår i: 2007 European Conference On Circuit Theory And Design. - 9781424413416 ; , s. 348-351
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Konferensbidrag (refereegranskat)abstract
- A least mean square (LMS) based calibration algorithm is proposed to calibrate most known error sources in 1.5 bit/stage pipelined ADCs, known to be immune to moderate comparator offsets. The error sources include linear gain errors, reference voltage errors, systematic offset errors and amplifier non-linear errors of each pipeline stage. LMS is used to estimate the error parameters in the digital domain. After estimation the proposed algorithm calibrate the pipelined ADC using the estimated parameter errors. Simulation results show that the proposed algorithm can improve the ENOB from 6.6 bits to 13.9 bits for a 14 bit 1.5 bits/stage pipelined ADC.
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