| 1. |
- Alfredsson, Jon, et al.
(författare)
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D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements
- 2007
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Ingår i: 2007 NORCHIP. - : IEEE conference proceedings. - 9781424415168 ; , s. 146-149
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Konferensbidrag (refereegranskat)abstract
- When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.
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| 2. |
- Axholt, Andreas, et al.
(författare)
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A 0.25W fully integrated class-d audio power amplifier in 0.35um CMOS
- 2007
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Ingår i: [Host publication title missing]. - 9781424415168 ; , s. 46-49
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Konferensbidrag (refereegranskat)abstract
- A fully integrated class-D audio power amplifier using Pulse Width Modulation (PWM) technique is presented. The output stage is an H-bridge with 5.75 min wide nMOS transistors and 15 min wide pMOS transistors, which can deliver up to 0.25 W-rms to an 16 ohm load. The chip measuring 1.2x2.4 mm(2), including pads, was fabricated in a 0.35 mu m CMOS process. It uses a single 3.3 V supply and a PWM carrier frequency of 2.5 MHz. The chip was designed and simulated with Cadence IC design tools as a student project in the course IC-project and verification at Lund University. The chip was verified and works well with a measured THD+N of 0.5% and efficiency of 76% at 0.25 W-rms output power into 16 ohm.
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| 3. |
- Chen, Jian, et al.
(författare)
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Sizing of MOS device in LC-tank oscillators
- 2007
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Ingår i: 2007 Norchip. - 9781424415168 ; , s. 90-95
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Konferensbidrag (refereegranskat)abstract
- Since previous publications show conflicting results about sizing device, relationship between device size and 1/f(2) phase noise is studied and closed-form equations are derived in order to help designers to size devices in LC-tank oscillators for good phase noise performance. The analysis is divided into two steps. Firstly, periodic noise transfer functions of each VCO noise source to the output of switch FETs are derived, and the impact of sizing on these functions is discussed. Secondly, phase noise equations are derived with these functions. Experiments show that phase noise predicted by the equations agrees with that from simulations.
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| 4. |
- Cijvat, Pieternella, et al.
(författare)
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A GaN HEMT power amplifier with variable gate bias for envelope and phase signals
- 2007
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Ingår i: [Host publication title missing]. - Aalborg, Denmark : Institute of Electrical and Electronics Engineers (IEEE). - 9781424415168 ; , s. 108-111
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Konferensbidrag (refereegranskat)abstract
- This paper describes the design, simulation and measurement of a GaN power amplifier suitable for envelope and phase signal combination. The low-frequency envelope signal is used to vary the gate (bias) voltage of the device, resulting in a pulse width modulated drain voltage, while modulation of supply voltage or current is avoided. The test circuit is implemented using a discrete GaN HEMT power amplifier and discrete surface-mount passive components assembled on a PCB. Measurements showed a maximum drain efficiency of 59% at 360 MHz, at an output power of 29 dBm. The output power as a function of the gate bias voltage varied between 3 and 29 dBm, with the drain efficiency varying between 6 and 59%.
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| 5. |
- Kristensen, Fredrik, et al.
(författare)
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Low Complexity Real-Time Feature Extraction Using Image Projections
- 2007
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Ingår i: [Host publication title missing]. - 9781424415168 ; , s. 120-123
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Konferensbidrag (refereegranskat)abstract
- In this paper it is shown how low complexity image projections can be used to replace the much more memory demanding functions morphology and labeling. The image projections are intended to be used in an automatic real-time surveillance system to detect objects and extract features. The projection unit operates directly on the binary motion mask from the segmentation unit and can extract location, size and center of gravity of the detected objects. To increase the precision, multiple projections are calculated in the Y-direction of the motion mask. To verify the design a demonstrator has been implemented on a Xilinx FPGA, where the effect of different input settings can be evaluated in real-time. Compared to the previous solution with morpholoqy and labeling, the memory requirement is reduced from O(n(2)) to O(n).
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| 6. |
- Lawal, Najeem, et al.
(författare)
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Power-aware automatic constraint generation for FPGA based real-time video processing systems
- 2007
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Ingår i: 25th Norchip Conference, NORCHIP. - New York : IEEE conference proceedings. - 9781424415168 ; , s. 124-128
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Konferensbidrag (refereegranskat)abstract
- The introduction of embedded DSP blocks and embedded memory has made FPGAs an attractive architecture for implementation of real-time video processing systems. The big bottle neck of the FPGA compared to other programmable architectures is the complex programming model. This paper presents an automatic generation of placement and routing constraints for FPGA implementation of real-time video processing systems as one step to automate the programming model. The constraint generator targets lower power consumption, better resource utilization and reduced development time. Results show that a 28 % reduction in dynamic power can be achieved using the proposed approach over traditional logic to memory mapping.
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| 7. |
- Sarmiento, David M., et al.
(författare)
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Low power tunable CMOS I-UWB transmitter design
- 2007
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Ingår i: 2007 Norchip. - 9781424415168 ; , s. 116-119
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Konferensbidrag (refereegranskat)abstract
- In this paper an on-chip tunable Impulse-Ultra Wide Band Transmitter is presented. It is capable of modifjing the power emission to comply with the FCC regulations at different pulse rates up to 300 NMz using two external controls. The maximum power consumption is 1.2 mW and 142 mu W at 300 NMz and 10 AM PRF respectively with a leakage current of 100 nA. The prototype has been designed in 0.18 UMC technology and placed in a QFN lead-less package.
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