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Sökning: L773:9781424441426

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1.
  • Holsmark, Rickard, et al. (författare)
  • HiRA : A methodology for deadlock free routing in hierarchical networks on chip
  • 2009
  • Ingår i: Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on. - : IEEE Computer Society. - 9781424441426 ; , s. 2-11
  • Konferensbidrag (refereegranskat)abstract
    • Complexity of designing large and complex NoCs can be reduced/managed by using the concept of hierarchical networks. In this paper, we propose a methodology for design of deadlock free routing algorithms for hierarchical networks, by combining routing algorithms of component subnets. Specifically, our methodology ensures reachability and deadlock freedom for the complete network if routing algorithms for subnets are deadlock free. We evaluate and compare the performance of hierarchical routing algorithms designed using our methodology with routing algorithms for corresponding flat networks. We show that hierarchical routing, combining best routing algorithm for each subnet, has a potential for providing better performance than using any single routing algorithm. This is observed for both synthetic as well as traffic from real applications. We also demonstrate, by measuring jitter in throughput, that hierarchical routing algorithms leads to smoother flow of network traffic. A router architecture that supports scalable table-based routing is briefly outlined.
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2.
  • Weldezion, Awet Yemane, et al. (författare)
  • Scalability of Network-on-Chip Communication Architecture for 3-D Meshes
  • 2009
  • Ingår i: 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP. - NEW YORK : IEEE. - 9781424441426 ; , s. 114-123
  • Konferensbidrag (refereegranskat)abstract
    • Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologiesfor 3-D Network-on-Chips (NoC) using Through-Silicon-Was (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3-D NoC is examined under both communication architectures and compared to 2-D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.
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