| 1. |
- Abd El Ghany, M. A., et al.
(författare)
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Power efficient networks on chip
- 2009
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Ingår i: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. - 9781424450916 ; , s. 105-108
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Konferensbidrag (refereegranskat)abstract
- a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduce. The power consumption oy the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover. The power reduction technique is applied to different NoC architectures. The technique reduce. The power consumption oy the network by up to 41%. Whe. The power consumption oy the whole network includin. The interswich links and repeaters is taken into account. The overall power consumption is decreased by up to 33% at the maximum operating frequency oy the switch. The BFT architecture consume. The minimum power as compared to other NoC architectures.
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| 2. |
- Abd Elghany, M. A., et al.
(författare)
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High throughput architecture for OCTAGON network on chip
- 2009
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Ingår i: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. - : IEEE. - 9781424450916 ; , s. 101-104
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Konferensbidrag (refereegranskat)abstract
- High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increase. The throughput oy the network by 17% while preservin. The average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achiev. The proposed architecture is 2% oy the total power consumption oy the OCTAGON architecture.
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| 3. |
- Dixon, A., et al.
(författare)
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Digital self-aware charge pump calibration technique for frequency synthesizers
- 2009
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Ingår i: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. - : IEEE. - 9781424450916 ; , s. 743-746
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Konferensbidrag (refereegranskat)abstract
- As radio design complexity increases and features sizes decrease, more innovative solutions are explored to ensure analog circuit designs meet specifications. Digital calibration is an inexpensive and effective solution. A novel digital calibration technique to improve charge pump current mismatch in frequency synthesizers is presented. This method detect. The charge pump error by measurin. The low pass filter voltage oy the system forced to operate at a fixed phase error. A reference table developed from a mathematical model oy the system use. The measurement result to produce a digital control word. The digital control word acts on a charge pump array to correc. The error. The technique is implemented and tested in Matlab/Simulink for a case study frequency synthesizer. The calibration technique correct. The charge pump current absolute error to within 1.4% oy the nominal value. Additionally. The technique is exceptionally effective for correctin. The charge pump current mismatch to within 1%.
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