| 1. |
- Ahmad, Shakeel, 1977-, et al.
(författare)
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Two-tone PLL for on-chip IP3 test
- 2010
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Ingår i: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10). - : IEEE. - 9781424453085 ; , s. 3549-3552
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Konferensbidrag (refereegranskat)abstract
- This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.
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| 2. |
- Fritzin, Jonas, et al.
(författare)
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Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS
- 2010
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Ingår i: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France. - : IEEE. - 9781424453085 ; , s. 1907-1910
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Konferensbidrag (refereegranskat)abstract
- This paper presents reliability measurements of a differential Class-E power amplifier (PA) operating at 850MHz in 130nm CMOS. The RF performance of five samples was tested. At 1.1V, the PAs deliver +20.4–21.5dBm of output power with drain efficiencies and power-added efficiencies of 56–64% and 46–51%, respectively. After a continuous long-term test of 240 hours at elevated supply voltage of 1.4V, the output power dropped about 0.7dB.
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| 3. |
- Mesgarzadeh, Behzad, et al.
(författare)
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EMI reduction by resonant clock distribution networks
- 2010
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Ingår i: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France. - : IEEE. - 9781424453085 ; , s. 977-980
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Konferensbidrag (refereegranskat)abstract
- In today's automotive vehicles, electromagnetic interference (EMI) from electronic circuits has become a serious concern. The discussion in this paper proves that a clock signal generated by a resonant clock distribution network exhibits better EMI performance compared to that of a conventional buffer-driven clock network. This discussion is supported by analyzing different clock spectrums and using a simple model of simultaneous switching noise (SSN). According to simulation results presented in a 90-nm CMOS process, using a sinusoidal clock instead of a trapezoidal one, the magnitude of the first tone in the spectrum of SSN is reduced at least by 6.7 dB.
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| 4. |
- Naeem, Abdul, et al.
(författare)
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Scalability of Weak Consistency in NoC based Multicore Architectures
- 2010
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Ingår i: IEEE INT SYMP CIRC SYST PROC. - New York : IEEE. - 9781424453085 ; , s. 3497-3500
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Konferensbidrag (refereegranskat)abstract
- In Multicore Network-on-Chip, it is preferable to realize distributed but shared memory (DSM) in order to reuse the huge amount of legacy code and easy programming. Within DSM systems, memory consistency is a critical issue since it affects not only performance but also the correctness of programs. In this paper, we investigate the scalability of the weak consistency model, which may be implemented using a transaction counter. The experimental results compare synchronization latencies for various network sizes, topologies and lock positions in the network. Average synchronization latency rises exponentially for mesh and torus topologies as the network size grows. However, torus improves the synchronization latency in comparison to mesh. For mesh topology network average synchronization latency is also slightly affected by the lock position with respect to the network center.
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| 5. |
- Qureshi, Fahad, 1978-, et al.
(författare)
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Twiddle factor memory switching activity analysis of radix-22 and equivalent FFT algorithms
- 2010
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Ingår i: The IEEE International Symposium on Circuits and Systems (ISCAS) , Paris, 2010.. - : IEEE. - 9781424453092 - 9781424453085 ; , s. 4145-4148
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose equivalent radix-22 algorithms and evaluate them based on twiddle factor switching activity for a single delay feedback pipelined FFT architecture. These equivalent pipeline FFT algorithms have the same number of complex multipliers with the same resolution as the radix-22. It is shown that the twiddle factor switching activity of the equivalent algorithms is reduced with up to 40% for some of the equivalent algorithms derived for N = 256.
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| 6. |
- Wang, Peng, et al.
(författare)
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A 3.1-4.8-GHz energy-detector front-end for non-coherent OOK impulse-radio UWB
- 2010
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Ingår i: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems. - : IEEE. - 9781424453085 ; , s. 485-488
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Konferensbidrag (refereegranskat)abstract
- This paper proposes a 0-33.3Mb/s front-end of the energy detector for 3.1-4.8-GHz impulse-radio ultra-wideband (IR-UWB). Fully differential architecture with the non-coherent on-off-keying (OOK) modulation is adopted. Targeting at - 98dBm sensitivity, the low noise amplifier (LNA) is designed to achieve <3.5dB noise figure, <-10dB S11, and >15dB gain. Interleaved integrating scheme relaxes the implementation of digital circuits. Thanks to the duty-cycling, the front-end achieves 420pJ/bit energy efficiency for OOK modulation. The bias is generated by band-gap circuits. The layout design and verification are completed with Cadence Spectre using UMC 90nm CMOS.
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