| 1. |
- Abd El Ghany, M. A., et al.
(författare)
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Asynchronous BFT for low power networks on chip
- 2010
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Ingår i: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems. - : IEEE. - 9781424453092 ; , s. 3240-3243
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Konferensbidrag (refereegranskat)abstract
- Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the αdata equals 0.2 and the activity factor of the control signals is equal to 1/64 of the αdata. The total metal resources required to implement Asynchronous design is decreased by 12%.
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| 2. |
- Abd El Ghany, M. A., et al.
(författare)
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Power characteristics of networks on chip
- 2010
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Ingår i: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems. - : IEEE. - 9781424453092 ; , s. 3721-3724
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Konferensbidrag (refereegranskat)abstract
- Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch links and repeaters for BFT represents only 1% of the total power dissipation of the network. In addition of providing high throughput, the BFT is a power efficient topology for NoCs.
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| 3. |
- Chiragwandi, Zackary, 1968, et al.
(författare)
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Robustness of logic gates and reconfigurability of neuromorphic switching networks
- 2010
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Ingår i: Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS). - 0271-4302. - 9781424453092 ; , s. 1671-1674
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Konferensbidrag (refereegranskat)abstract
- Nanoparticle networks with functional molecular links that show current- voltage characteristics (IVC) with negative differential resistance (NDR) can be trained to perform XOR-AND logic gates (Husband et al. [1]; Skoldberg and Wendin [2]). In this work we investigate the robustness of the Nanocell network by removing links until desired logic gates no longer can be configured or operated within our simulation of the network. We present results for the robustness of XOR-AND configured (halfadder) Nanocells, as well as the effects of varying the IVC and NDR characteristics of the linker molecules.
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| 4. |
- Olsson, Thomas, et al.
(författare)
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A reconfigurable OFDM inner receiver implemented in the CAL dataflow language
- 2010
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Ingår i: IEEE International Symposium on Circuits and Systems. - 0271-4310 .- 2158-1525. - 9781424453092 ; , s. 2904-2907
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Konferensbidrag (refereegranskat)abstract
- This paper presents a reconfigurable inner receiver for the LTE, DVB-H, and IEEE802.11n (WLAN) radio systems, all of which are based on orthogonal frequency division multiplexing (OFDM). The receiver is implemented in the CAL language. An FPGA-based hardware implementation is synthesized from RTL generated from the CAL description. The purpose of our work is to investigate the feasibility of dataflow methodology for high-level description of digital radio transceivers.
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| 5. |
- Qureshi, Fahad, 1978-, et al.
(författare)
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Twiddle factor memory switching activity analysis of radix-22 and equivalent FFT algorithms
- 2010
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Ingår i: The IEEE International Symposium on Circuits and Systems (ISCAS) , Paris, 2010.. - : IEEE. - 9781424453092 - 9781424453085 ; , s. 4145-4148
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose equivalent radix-22 algorithms and evaluate them based on twiddle factor switching activity for a single delay feedback pipelined FFT architecture. These equivalent pipeline FFT algorithms have the same number of complex multipliers with the same resolution as the radix-22. It is shown that the twiddle factor switching activity of the equivalent algorithms is reduced with up to 40% for some of the equivalent algorithms derived for N = 256.
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| 6. |
- Rodriguez, Saul, et al.
(författare)
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An IIP2 Digital Calibration Technique for Passive CMOS Down-Converters
- 2010
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Ingår i: IEEE INT SYMP CIRC SYST PROC. - New York : IEEE. - 9781424453092 ; , s. 825-828
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Konferensbidrag (refereegranskat)abstract
- The IIP2 requirement in fully integrated direct-conversion receivers using FDD duplexing is prohibitively high and demands the use of an external filter in order to attenuate the leakage from the transmitter. This paper presents a digital calibration technique for passive CMOS down-converters that allows a direct conversion receiver achieve the requirements without external filtering. A Least-Mean-Square optimization algorithm is used in order to reduce the low-frequency second-order intermodulation product. The algorithm controls the digital calibration structures at the biasing of the passive mixer and adapts them until the second order intermodulation drops below the noise level. The method is tested by calibrating a 1.2-V 65nm CMOS passive mixer targeting UMTS/LTE applications at several corner conditions including worst case mismatches in the switching pairs.
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| 7. |
- Rong, Liang, et al.
(författare)
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A Switch Mode Resonating H-Bridge Polar Transmitter using RF Sigma Delta Modulation
- 2010
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Ingår i: IEEE INT SYMP CIRC SYST PROC. - 9781424453092 ; , s. 1911-1914
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Konferensbidrag (refereegranskat)abstract
- Using saturated power amplifier (PA) as the last stage, polar transmitter has the potential to be the most power efficient architecture to transmit large Peak-to-Average Ratio (PAR) signals. In this work, a polar transmitter using H-Bridge configured Class-D amplifiers is proposed. To fully exploit low voltage resource, maintain linearity and meet the spectrum mask requirements, RF Sigma-Delta Modulation (SDM) is used. An on-chip transformer based filter network is designed to filter out SDM noise and provide load matching. The system verification is carried out by using Matlab passband simulation on a 13dB PAR mobile WiMAX signal. Evaluation of noise shaping and spectral regrowth shows the proposed architecture can achieve -45dBc/10kHz ACPR in a 140MHz bandwidth range. This provides a solid ground for the circuit design work.
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