| 1. |
- Jalili, Armin, et al.
(författare)
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Calibration of high-resolution flash ADCS based on histogram test methods
- 2010
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Ingår i: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. - : IEEE. - 9781424481552 ; , s. 114-117
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.
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| 2. |
- Latif, Khalid, et al.
(författare)
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Resource-aware task allocation and scheduling for SegBus platform
- 2010
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Ingår i: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings. - 9781424481552 - 9781424481576 ; , s. 523-526
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Konferensbidrag (refereegranskat)abstract
- In this work, we propose an integrated task allocation and scheduling mechanism to minimize the resource contention and the processing latency for application running on the SegBus platform. The transactions are classified as local and cross border SPLIT transactions. The hybrid scheduling approach implemented by hierarchal arbiter code structure shows significant improvement in system performance. The interrupt scheduling has been implemented to further enhance system performance. A H.264 video encoder application has been used to verify the proposed technique, showing a large improvement in system throughput.
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| 3. |
- Rodriguez, Saul, et al.
(författare)
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A 2.3-GHz to 5.8-GHz CMOS receiver front-end for WiMAX/WLAN
- 2010
-
Ingår i: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings. - 9781424481552 ; , s. 1068-1071
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Konferensbidrag (refereegranskat)abstract
- This paper presents a wideband, direct-conversion radio receiver front-end that targets all WiMAX/WLAN bands from 2.3-GHz to 5.8-GHz. The receiver front-end is fabricated in 0.18-μm CMOS and achieves a gain of 25 dB, noise figure of 6 dB, and IIP3 of -6 dBm while dissipating 28 mW from a 1.8-V power supply. This performance is achieved while using only two integrated inductors.
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