| 1. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS
- 2010
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Ingår i: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10. - Tampere : www.ieee.org. - 9781424489718 - 9781424489725 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.
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| 2. |
- Afzal, Nadeem, et al.
(författare)
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Study of modified noise-shaper architectures for oversampled sigma-delta DACs
- 2010
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Ingår i: NORCHIP, 2010. - : IEEE. - 9781424489725 ; , s. 1-4
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by maintaining low-complexity of noise shaper. The complexity of the subDAC is yet a parameter, directly related to the number of output bits from the noise shaper. Two different architectures are investigated with respect to subDAC complexity and noise shaper complexity. It is shown that the required number of DAC unit elements (DUE) can be reduced to half.
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| 3. |
- Gruian, Flavius, et al.
(författare)
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NoC-based CSP support for a Java chip multiprocessor
- 2010
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Ingår i: [Host publication title missing]. - 9781424489725
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Konferensbidrag (refereegranskat)abstract
- In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. A CMP architecture of three processors is implemented and tested on an FPGA, showing a 15% increase in device area without performance penalties. Compared to shared memory-based communication, our NoC-based solution is between 2.3 and 11.5 times faster, depending on the communication and memory configuration.
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| 4. |
- Jalili, Armin, et al.
(författare)
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Calibration of sigma-delta analog-to-digital converters based on histogram test methods
- 2010
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Ingår i: NORCHIP, 2010. - : IEEE. - 9781424489725 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which highspeed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied. It is shown that the calibration technique can cope with errors that occur in the feedback digital-to-analog converter (DAC) and the input accumulator. Behavioral-level simulation results show an improvement of in effective number of bits (ENOB) from 6.6 to 11.3. Fairly large offset and gain errors have been introduced which illustrates a robust calibration technique.
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| 5. |
- Lu, Ping, et al.
(författare)
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A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS
- 2010
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Ingår i: [Host publication title missing]. - 9781424489725
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Konferensbidrag (refereegranskat)abstract
- A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.
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| 6. |
- Najari, Omid, et al.
(författare)
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Wideband inductorless LNA employing simultaneous 2nd and 3rd order distortion cancellation
- 2010
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Ingår i: Proc. Norchip. - Tampere : IEEE. - 9781424489725
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Konferensbidrag (refereegranskat)abstract
- This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz-5GHz.
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| 7. |
- Sadeghifar, Mohammad Reza, et al.
(författare)
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A higher Nyquist-range DAC employing sinusoidal interpolation
- 2010
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Ingår i: NORCHIP, 2010. - : IEEE. - 9781424489725 ; , s. 1-4
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.
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| 8. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
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Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
- 2010
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Ingår i: [Host publication title missing]. - 9781424489725
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Konferensbidrag (refereegranskat)abstract
- This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub- VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of 100Ksamples/sec to 1Msamples/s, as it dissipates less energy than any other implementation in this speed range.
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| 9. |
- Zhang, Dai, et al.
(författare)
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Design of CMOS sampling switch for ultra-low power ADCs in biomedical applications
- 2010
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Ingår i: NORCHIP 2014. - Tampere : IEEE. - 9781424489718 - 9781424489725 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakage-reduction has been designed for a 10-bit 1-kS/s successive approximation (SA) ADC in a standard 130 nm CMOS process. Post-layout simulation shows that the ADC with the proposed switch offers an effective number of bits (ENOB) of 9.5 while consuming only 64 nW.
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