| 1. |
- Ansari, Muhammad Adeel, et al.
(författare)
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Diode based charge pump design using 0.35μm technology
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - : IEEE. - 9781424489732 ; , s. 5669437-
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Konferensbidrag (refereegranskat)abstract
- A high voltage charge pump design is being presented in this paper. The design is based on Dickson charge pump, constructed with diodes by using AMS 0.35μm technology. The innovation is made in Dickson charge pump i.e. charge control PMOS transistor is used in each stage of charge pump. PMOS transistor is used in series with charging capacitor which reduces the power consumption during the clock transition by controlling the time constant of each stage. The resistance between drain to source of PMOS transistor increases the time constant during the charging of the capacitor placed in each stage of charge pump. The output voltage of about 5.693V is achieved by the six stages of Dickson charge pump at no-load which reduces to 5.537V with the six stages of proposed charge pump but the power during the input clock transition is reduced from 340.5μw (consumed by Dickson charge pump) to 28.85 μW (consumed by the proposed modified charge pump). Some other results are also discussed in this paper, which are achieved on different load resistances.
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| 2. |
- Chen, Xiaowen, et al.
(författare)
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Multi-FPGA Implementation of a Network-on-Chip Based Many-core Architecture with Fast Barrier Synchronization Mechanism
- 2010
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Ingår i: Proceedings of the IEEE Norchip Conference. - 9781424489732
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose a fast barrier synchronization mechanism, targetingNetwork-on-Chip based manycore architectures. Its salient feature is that, once thebarrier condition is reached, the "barrier release" acknowledgement is routed to all processor nodes in a broadcast way in order to save area by avoiding storing source node information and to minimize completion time by eliminating serialization of barrierreleasing. Then, we construct a multi-FPGA platform using Xilinx® Virtex 5 as FPGA chipsand implement a NoC based many-core architecture on it. FPGA utilization and simulation results show that our mechanism demonstrates both area and performance advantages over the barrier synchronization counterpart with unicast barrier releasing.
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| 3. |
- Guang, Liang, et al.
(författare)
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Hierarchical power monitoring on NoC - a case study for hierarchical agent monitoring design approach
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - 9781424489732 ; , s. 5669428-
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Konferensbidrag (refereegranskat)abstract
- A case study is presented for hierarchical agent monitoring design approach, which provides a high level abstraction for designing monitoring functions on massively parallel and distributed systems. The case study features hierarchical power monitoring on NoC platforms, where each level of agents perform specific monitoring operations based on their granularity. The monitoring hierarchy and operations are specified by a formal language for consistent and non-ambiguous system design. Various benchmarks are mapped onto NoCs, running with hierarchical power monitoring agents. Quantitative evaluations are performed in terms of energy efficiency, communication latency, and silicon overhead.
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| 4. |
- Imran, Muhammad, et al.
(författare)
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Exploration of Target Architecture for aWireless Camera Based Sensor Node
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - : IEEE conference proceedings. - 9781424489732 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is based on conducting all processing locally at the sensor node and transmitting only the final results. Our research is focused on partitioning the vision processing tasks between Senor node and central base station. In this paper we have added the exploration dimension to perform some of the vision tasks such as image capturing, background subtraction, segmentation and Tiff Group4 compression on FPGA while communication on microcontroller. The remaining vision processing tasks i.e. morphology, labeling, bubble remover and classification are processed on central base station. Our results show that the introduction of FPGA for some of the visual tasks will result in a longer life time for the visual sensor node while the architecture is still programmable.
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| 5. |
- Kianpour, I., et al.
(författare)
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An 8-bit 166nw 11.25 kS/s 0.18um two-step-SAR ADC for RFID applications using novel DAC architecture
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - 9781424489732 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- SAR ADCs have been mostly used for moderate-speed, moderate-resolution applications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC. In this paper an ultra low power two-step-SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with no static current and a dual-stage (Resistor-string / capacitive dividing) architecture as digital-to-analog converter (DAC). In this DAC architecture fine search will be performed by only two C and 15C capacitors which reduced the silicon area significantly. The circuit designed in 0.18um CMOS technology and simulations show that the 8-bit ADC, consumes almost 166nW at 11.25kS/s. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison with its charge redistribution counterpart.
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| 6. |
- Malik, Omer, et al.
(författare)
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High Level Synthesis Framework for a Coarse Grain Reconfigurable Architecture
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - 9781424489732 ; , s. 5669439-
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Konferensbidrag (refereegranskat)abstract
- A High Level Synthesis Framework for mapping DSP algorithms on a Coarse Grain Reconfigurable Architecture is presented. Behavioral specification of the algorithm in C is specified with pragmas in comments and the tool generates configware after performing timing and synchronization synthesis. Pragmas identify SIMD type concurrency and sweep the architectural space with allocation and binding annotations to produce implementations from fully serial to fully parallel. This allows user to stay at algorithmic level and guide the HLS tool to search a restricted architectural space bounded by the pragmas thus making the synthesis process more efficient and predictable.
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| 7. |
- Meganathan, D., et al.
(författare)
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A low-power, medium-resolution, high-speed CMOS pipelined ADC
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - 9781424489732 ; , s. 5669438-
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Konferensbidrag (refereegranskat)abstract
- This paper presents the systematic design approach of a low-power, medium-resolution, high-speed pipelined Analog-to-Digital Converter (ADC). The ADC is implemented in 180nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB and effective number of bits of 9.64-bits at sampling speed of 50MHz with an input signal frequency of 4MHz. The peak differential-nonlinearity of the converter is 0.28/-0.17LSB and integral-nonlinearity of the converter is +0.42/-0.41LSB. The proposed 10-bit, 50MS/sec pipelined ADC consumes 24.5mW amount of power from 1.8V supply.
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| 8. |
- Rahmani, Amir M., et al.
(författare)
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An efficient VFI-based NoC architecture using Johnson-encoded Reconfigurable FIFOs
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - 9781424489732
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Konferensbidrag (refereegranskat)abstract
- In this paper, a Johnson-encoded Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The proposed FIFO which can be used to interface modules in Voltage/Frequency Islands (VFI) based Networks-on-chip, is capable of alleviating the excessive energy consumption and high performance overhead of the conventional bi-synchronous FIFOs. The FIFO is scalable and synthesizable in synchronous standard cells. In addition, a technique for mesochronous adaptation of the proposed FIFO is presented. Our extensive experiments show significant power and performance improvements compared to non-reconfigurable architectures.
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| 9. |
- Rahmani, Amir M, et al.
(författare)
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Research and practices on 3D networks-on-chip architectures
- 2010
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Ingår i: 28th Norchip Conference, NORCHIP 2010. - 9781424489732
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Konferensbidrag (refereegranskat)abstract
- To continue the growth of the number of transistors on a chip, the 3D IC practice, where multiple silicon layers are stacked vertically, is emerging as a revolutionary technology. Partitioning a larger die into smaller segments and then stacking them in a 3D integration can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible compared to intra-wafer distances which substantially reduce global wiring length in 3D chips. This progress has introduced novel architectures and new challenges for high-performance power-aware design exploration. In this paper, we outline the opportunities and challenges associated with three-dimensional networks-on-chip architectures, under consideration for different design metrics. In this context, we categorize and present several alternatives for 3D NoC architectures and we investigate and summarize the impact of these architectures on various system characteristics.
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| 10. |
- Shami, Muhammad Ali, 1980-, et al.
(författare)
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An improved self-reconfigurable interconnection scheme for a Coarse Grain Reconfigurable Architecture
- 2010
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Ingår i: NORCHIP 2010. - 9781424489732
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Konferensbidrag (refereegranskat)abstract
- An improved Dynamic, Partial and self reconfigurable interconnection network (Hybrid-2 Network) is presented for Dynamically Reprogrammable Resource Array (DRRA), which is a Coarse Grain Reconfiguration Architecture (CGRA). To justify the design decision, Hybrid-2 network implementation is compared against the possible implementations using Multiplexer, NoC, Crossbar and already published Hybrid-1 interconnection network. Results shows that newly presented Hybrid-2 Interconnection network take (1.08x, 0.104x, 0.212x and 0.681x) the area, (1x, 0.037x, 0.026x and 0.107x) the configuration bits of Multiplexer, NoC, Crossbar and Hybrid-1 Implementation respectively. Hybrid-2 network is also 2.87x and 5.86x faster than Multiplexer and Hybrid-1 networks.
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