| 1. |
- Alipour, Mehdi, et al.
(författare)
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Exploring the performance limits of out-of-order commit
- 2017
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Ingår i: Proc. 14th Computing Frontiers Conference. - New York : ACM Press. - 9781450344876 ; , s. 211-220
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Konferensbidrag (refereegranskat)abstract
- Out-of-order execution is essential for high performance, general-purpose computation, as it can find and execute useful work instead of stalling. However, it is limited by the requirement of visibly sequential, atomic instruction execution --- in other words in-order instruction commit. While in-order commit has its advantages, such as providing precise interrupts and avoiding complications with the memory consistency model, it requires the core to hold on to resources (reorder buffer entries, load/store queue entries, registers) until they are released in program order. In contrast, out-of-order commit releases resources much earlier, yielding improved performance with fewer traditional hardware resources. However, out-of-order commit is limited in terms of correctness by the conditions described in the work of Bell and Lipasti. In this paper we revisit out-of-order commit from a different perspective, not by proposing another hardware technique, but by examining these conditions one by one and in combination with respect to their potential performance benefit for both non-speculative and speculative out-of-order commit. While correctly handling recovery for all out-of-order commit conditions currently requires complex tracking and expensive checkpointing, this work aims to demonstrate the potential for selective, speculative out-of-order commit using an oracle implementation without speculative rollback costs. We learn that: a) there is significant untapped potential for aggressive variants of out-of-order commit; b) it is important to optimize the commit depth, or the search distance for out-of-order commit, for a balanced design: smaller cores can benefit from shorter depths while larger cores continue to benefit from aggressive parameters; c) the focus on a subset of out-of-order commit conditions could lead to efficient implementations; d) the benefits for out-of-order commit increase with higher memory latency and works well in conjunction with prefetching to continue to improve performance.
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| 2. |
- Ortiz, Gabriel, 1990, et al.
(författare)
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Instruction level energy model for the Adapteva Epiphany multi-core processor
- 2017
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Ingår i: 14th ACM International Conference on Computing Frontiers, CF 2017, Siena, Italy, 15-17 May 2017. - New York, NY, USA : ACM. - 9781450344876 ; , s. 380-384
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Konferensbidrag (refereegranskat)abstract
- Processor energy models can be used by developers to estimate, without the need of hardware implementation or additional measurement setups, the power consumption of so ware applications. Furthermore, these energy models can be used for energy-aware compiler optimization. is paper presents a measurement-based instruction-level energy characterization for the Adapteva Epiphany processor, which is a 16-core shared-memory architecture connected by a 2D network-on-chip. Based on a number of microbenchmarks, the instruction-level characterization was used to build an energy model that includes essential Epiphany instructions such as remote memory loads and stores. To validate the model, an FFT application was developed. is validation showed that the energy estimated by the model is within 0.4% of the measured energy.
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| 3. |
- Otoom, Mwaffaq, et al.
(författare)
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Using personality metrics to improve cache interference management in multicore processors
- 2017
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Ingår i: 14th ACM International Conference on Computing Frontiers, CF 2017, Siena, Italy, 15-17 May 2017. - New York, NY, USA : ACM. - 9781450344876 ; , s. 251-254
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Konferensbidrag (refereegranskat)abstract
- The trend of increasing the number of cores in a processor will lead to certain challenges, among which the fact that more cores issue more memory requests and this in turn will increase the competition, or interference, for shared resources such as the Last-Level Cache (LLC). In this work we focus on the cache interference while executing Decision Support System queries, which is a common case for a Data Center scenario. We study the co-execution of different queries from the TPC-H benchmark using the PostgreSQL DBMS system on a multicore with up to 16 cores and different LLC configurations. In addition to the working set metric, to better understand the effects of co-execution, we develop two new "personality" metrics to classify the behavior of the queries in co-execution: social and sensitive metrics. These metrics can be used to manage the cache interference and thus improve the co-execution performance of the queries.
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| 4. |
- Zhang, J., et al.
(författare)
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RAGuard: A hardware based mechanism for backward-edge control-flow integrity
- 2017
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Ingår i: 14th ACM International Conference on Computing Frontiers, CF 2017, Siena, Italy, 15-17 May 2017. - New York, NY, USA : ACM. - 9781450344876 ; , s. 27-34
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Konferensbidrag (refereegranskat)abstract
- Control-flow integrity (CFI) is considered as a general and promising method to prevent code-reuse attacks, which utilize benign code sequences to realize arbitrary computation. Cur rent approaches can efficiently protect Control-flow transfers caused by indirect jumps and function calls (forward-edge CFI). However, they cannot effectively protect Control-flow caused by the function return (backward-edge CFI). The reason is that the set of return addresses of the functions that are frequently called can be very large, which might bend the backward-edge CFI. We address this backward-edge CFI problem by proposing a novel hardware-assisted mechanism (RAGuard) that binds a message authentication code to each return address and enhances security via a physical unclonable function and a hardware hash function. The message authentication codes can be stored on the program stack with return address. RAGuard hardware automatically verifies the integrity of return addresses. Our experiments show that for a subset of the SPEC CPU2006 benchmarks, RAGuard incurs 1.86% runtime overheads on average with no need for OS support.
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