| 1. |
- Abbas, Muhammad, et al.
(författare)
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Computational and Implementation Complexity of Polynomial Evaluation Schemes
- 2011
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Ingår i: Proceedings of NORCHIP, 2011 Date:14-15 Nov. 2011. - : IEEE conference proceedings. - 9781457705151 - 9781457705144 ; , s. 1-6
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Konferensbidrag (refereegranskat)abstract
- In this work, we consider the computational complexity of different polynomial evaluation schemes. By considering the number of operations of different types, critical path, pipelining complexity, and latency after pipelining, high-level comparisons are obtained. These can then be used to short list suitable candidates for an implementation given the specifications. Not only multiplications are considered, but they are divided into data-data multiplications, squarers, and data-coefficient multiplications, as the latter can be optimized depending on implementation architecture and application.
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| 2. |
- Abdulaziz, Mohammed, et al.
(författare)
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A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes less power. The DCO core adopts an improved source-varactor LC resonant tank to achieve a 20KHz frequency resolution. With the help of an additional ΔΣ modulator, the final frequency resolution is 625Hz. This work is simulated in 90nm CMOS process technology and consumes 7.6mW (DCO occupies 97.4%) under the power supply of 1.2V.
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| 3. |
- Alam, Syed Asad, 1984-, et al.
(författare)
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Implementation of Narrow-Band Frequency-Response Masking for Efficient Narrow Transition Band FIR Filters on FPGAs
- 2011
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Ingår i: NORCHIP, 2011. - : IEEE conference proceedings. - 9781457705144 - 9781457705151 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- The complexity of narrow transition band FIR filters is highand can be reduced by using frequency response masking (FRM) techniques. Thesetechniques use a combination of periodic model filters and masking filters. Inthis paper, we show that time-multiplexed FRM filters achieve lowercomplexity, not only in terms of multipliers, but also logic elements compared to time-multiplexed singlestage filters. The reduced complexity also leads to a lower power consumption. Furthermore, we show that theoptimal period of the model filter is dependent on the time-multiplexing factor.
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| 4. |
- Dasalukunte, Deepak, et al.
(författare)
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Complexity analysis of IOTA filter architectures in Faster-than-Nyquist multicarrier systems
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- This paper has evaluated the overhead requirements for IOTA pulse shaping filters employed in faster-than-Nyquist multicarrier systems. Faster-than-Nyquist signaling has shown the promise of improving bandwidth efficiency, but comes at the cost of increased processing complexity in the transceiver. The IOTA filter being one of the blocks contributing for the processing overhead, different architectural options have been evaluated. A comparison is drawn between the architectures of the IOTA filter and the suitable architecture with moderate hardware overhead is chosen for implementation.
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| 5. |
- Källström, Petter, et al.
(författare)
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Magnitude Scaling for Increased SFDR in DDFS
- 2011
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Ingår i: 29th Norchip Conference, Lund, Sweden, 14-15 November 2011. - : IEEE. - 9781457705151 - 9781457705144 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- When generating a sine table to be used in, e.g., frequency synthesis circuits, a widely used way to assign the table content is to simply take a sine wave with the desired amplitude and quantize it using rounding.This results in uncontrolled rounding of up to 0.5 LSB, causing some noise.In this paper we present a method for increasing the signal quality, simply by adjust the amplitude within a ±0.5 range from the intended. This will not affect the maximum value of the sinusoid, but can increase the spurious free dynamic range with some dB.
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| 6. |
- Latif, Khalid, et al.
(författare)
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A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip
- 2011
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Ingår i: Proc. NORCHIP. - United States : IEEE. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- A fault in one component of Networks-on-Chip (NoC) based system makes the fault-free connected units out of use and this in turn leads to considerable performance degradation. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. It is indispensable step needed to be taken in order to implement the reliable on-chip systems especially with nano-scale technologies. In this paper, we present a technique to recover healthy processing elements for NoC architectures in case of associated routers failure by using the Partial Virtual-Channel Sharing (PVS) approach. The proposed architecture divides the network into cluster regions, where each cluster comprises of two nodes. Each node in a cluster provides a backup data-path for other node in the cluster. Each processing element can use the backup data-path to transmit and receive the packets in case of corresponding router failure. The simulation results show that the proposed architecture has low hardware overheads.
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| 7. |
- Liu, Xiaodong, et al.
(författare)
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Highly linear direct conversion receiver using customized on-chip balun
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- This paper presents a highly linear radio frequency receiver front-end with on-chip balun for cellular application at 2GHz in 65nm CMOS technology. Based on direct conversion architecture, the implemented front-end comprises a customized on-chip balun for single-ended to differential signal conversion, a differential common-gate low noise amplifier and voltage mode quadrature passive mixer. The simulated in-band compression point is -0.5dBm and third order input intercept point is +6.2dBm. An out-of-band blocker compression point up to +4.8dBm and third order input intercept point of +16dBm are achieved thanks to the frequency translation filtering technique. The low-noise amplifier consumes 3mA current using 1.8V supply. The overall noise figure including balun loss, low-noise amplifier, mixer and a simplified model of a baseband filter is 3.8dB.
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| 8. |
- Löfgren, Johan, et al.
(författare)
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On Hardware Implementation of Radix 3 and Radix 5 FFT Kernels for LTE systems
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- Abstract in UndeterminedThis paper treats the hardware architecture andimplementation of mixed radix FFTs with cores of radix 3 andradix 5 in addition to the standard radix 2 core. The implementationflow graphs of the higher radix cores are presentedtogether with a description of how these cores afTect a pipelinedFFT implementation. It is shown that the mixed radix FFT ismore expensive than the radix 2 implementation - a mixed radixFFT of 1200 points require 36 real multipliers in a pipelinedimplementation whereas a 2048 radix 2 FFT needs 30 realmultipliers. However, half of the multipliers in the mixed radixcase can be constant. Therefore it is still feasible to use the mixedradix FFT if an algorithm calls for it.
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| 9. |
- Meraji, Reza, et al.
(författare)
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Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology.
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| 10. |
- Prabhu, Hemanth, et al.
(författare)
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A GALS ASIC implementation from a CAL dataflow description
- 2011
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Ingår i: IEEE. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations. The hardware-software co-design and Globally Asynchronous Locally Synchronous (GALS) design at a higher level of abstraction provides more freedom for design-space exploration and reduced design time. Performance is evaluated by a reference design, Orthogonal Frequency-Division Multiplexing (OFDM) multi-standard channel estimator based on robust Minimum Mean-Square Error (MMSE) algorithm. Higher throughput is attained due to inherent parallelism in CAL dataflow and reduced design time for GALS implementation.
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