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| 2. |
- Dasalukunte, Deepak, et al.
(författare)
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A 0.8mm2 9.6mW Implementation of a Multicarrier Faster-Than-Nyquist Signaling Iterative Decoder in 65nm CMOS
- 2012
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Ingår i: [Host publication title missing]. - 1930-8833. - 9781467322126 ; , s. 173-176
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Konferensbidrag (refereegranskat)abstract
- This paper presents a decoder for multi-carrier modulated signals employing Faster-than-Nyquist (FTN) signaling. FTN signaling is a method of improving bandwidth efficiency at the expense of higher processing complexity in the transceiver. The decoder can switch between orthogonal and FTN signaling modes and exploits channel properties to improve bandwidth efficiency. The decoder is fabricated in a 65nm CMOS process and occupies an area of 0.8mm2, with a power consumption of 9.6mW at 1.2V when clocked at 100MHz. To the best of our knowledge, those measurement results are from the first-ever silicon implementation of a decoder for FTN signaling.
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- Lemme, Max C.
(författare)
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Graphene for microelectronics : Can it make a difference?
- 2012
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Ingår i: 2012 Proceedings of the ESSCIRC (ESSCIRC). - : IEEE. - 9781467322126 ; , s. 25-27
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Konferensbidrag (refereegranskat)abstract
- Benchmarking figures for graphene show remarkable properties like ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs [1, 2]. When graphene is integrated and processed, however, defects in the graphene and its dielectric environment dominate device performance [3, 4]. Furthermore, the lack of a band gap limits the applicability of graphene field effect transistors (GFETs) for logic applications. Yet, there are many options for graphene to make a difference in the future of microelectronics, many of which can be attributed to the More than Moore domain defined in the ITRS. These will be discussed in this talk.
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| 5. |
- Zhang, Dai, et al.
(författare)
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A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s
- 2012
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Ingår i: ESSCIRC, 2012. - : Institute of Electrical and Electronics Engineers. - 9781467322119 - 9781467322126 ; , s. 369-372
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Konferensbidrag (refereegranskat)abstract
- This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.
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