| 1. |
- Afzal, Nadeem, et al.
(författare)
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Power efficient arrangement of oversampling sigma-delta DAC
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322218 - 9781467322225 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.
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| 2. |
- Alvbrant, Joakim, 1973-, et al.
(författare)
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Study and Simulation Example of a Redundant FIR Filter
- 2012
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Ingår i: Proceedings 30th Norchip Conference. - : IEEE. - 9781467322225 - 9781467322218 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a study and simulation results of the structure and design of a redundant finite-impulse response (FIR) filter. The filter has been selected as an illustrative example for biologically-inspired circuits, but the structure can be generalized to cover other signal processing systems. In the presented study, we elaborate on signal processing properties of the filter if we apply a redundant architecture were different computing paths can be utilized. An option is to utilize different computing paths as inspired by biological architectures (BIAs). We present typical simulation results for a low-pass filter illustrating the trade-offs and costs associated with this architecture.
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| 3. |
- Duong, Quoc-Tai, et al.
(författare)
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Wideband RF Detector Design for High Performance On-Chip Test
- 2012
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Ingår i: NORCHIP 2012. - : IEEE. - 9781467322225 - 9781467322218 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- A wideband, high dynamic range RF amplitude detector design aimed at on-chip test is presented. Boosting gain and sub-ranging techniques are applied to the detection circuit to increase gain over the full range of input amplitudes without compromising the input impedance. Followed by a variable gain amplifier (VGA) and a 9-bit A/D converter the RF detector system, designed in 65 nm CMOS, achieves in simulation the minimum detectable signal of -58 dBm and 63 dB dynamic range over 0.5 GHz - 9 GHz band with input impedance larger than 4 kΩ. The detector is intended for on-chip calibration and the attained specifications put it among the reported state-of-the-art solutions.
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| 4. |
- Harikumar, Prakash, et al.
(författare)
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An Analog Receiver Front-End for Capacitive Body-Coupled Communication
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322225 - 9781467322218 ; , s. 1-4
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.
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| 5. |
- Lu, Ping, et al.
(författare)
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A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
- 2013
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Ingår i: NORCHIP 2012. - 9781467322218 - 9781467322232
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Konferensbidrag (refereegranskat)abstract
- Two branches of gated ring oscillators (GRO) act as the delay lines in 2-dimension Vernier time-to-digital converter (TDC). The proposed architecture reduces dramatically the inherent latency of vernier structure. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been simulated in 90nm CMOS technology. Operating from 50MHz reference frequency, it achieves a resolution better than 2ps assuming a signal bandwidth of 1.56MHz (OSR=16), for a minimum current consumption of 1.8mA from 1.2V.
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| 6. |
- Mand, Nowshad Painda, et al.
(författare)
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Artificial neural network emulation on NOC based multi-core FPGA platform
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322218 ; , s. 6403122-
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Konferensbidrag (refereegranskat)abstract
- With the emergence of Multi-Core platforms, brain emulation in the form of Artificial Neural Nets has been announced as one of the important key research area. However, due to large non-linear growth of inter-neuron connectivity, direct mapping of ANNs to silicon structures is very difficult due to communication bottleneck.
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| 7. |
- Mao, Jia, et al.
(författare)
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A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applications
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322218 ; , s. 6403099-
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Konferensbidrag (refereegranskat)abstract
- This paper presents a 3-5 GHz, high output amplitude, carrier-less based Ultra Wideband (UWB) transmitter for wirelessly powered RFID application. The UWB transmitter consists of a baseband pulse generator, a driver amplifier and an output on-chip filter. The baseband pulse generator and the driver amplifier are designed as zero DC power consuming circuit, which enables scalable power with the pulse rate. IC pad and bonding wire parasitics are considered to be absorbed as part of output filtering network, realizing package co-design. The simulation result shows that the proposed transmitter radiates 2.34 pJ/pulse energy with 1.63 V pulse amplitude. The total energy consumption under 1.8 V power supply is 18 pJ/pulse, corresponding to 13% energy efficiency.
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| 8. |
- Saljooghi, Vahid, et al.
(författare)
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Configurable RTL Model for Level-1 Caches
- 2012
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Ingår i: Proceedings of NORCHIP, Copenhagen, Denmark, Nov. 11-12. - 9781467322218
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Konferensbidrag (refereegranskat)abstract
- Level-1 (L1) cache memories are complex circuits that tightly integrate memory, logic, and state machines near the processor datapath. During the design of a processor-based system, many different cache configurations that vary in, for example, size, associativity, and replacement policies, need to be evaluated in order to maximize performance or power efficiency. Since the implementation of each cache memory is a time-consuming and error-prone process, a configurable and synthesizable model is very useful as it helps to generate a range of caches in a quick and reproducible manner. Comprising both a data and instruction cache, the RTL cache model that we present in this paper has a wide array of configurable parameters. Apart from different cache size parameters, the model also supports different replacement policies, associativities, and data write policies. The model is written in VHDL and fits different processors in ASICs and FPGAs. To show the usefulness of the model, we provide an example of cache configuration exploration.
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| 9. |
- Svärd, Daniel, et al.
(författare)
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A Readout Circuit for an Uncooled IR Camera With Mismatch and Self-Heating Compensation
- 2012
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Ingår i: NORCHIP 2012. - : IEEE. - 9781467322218 - 9781467322232 - 9781467322225 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- This paper presents a readout integrated circuit for an infrared focal plane array intended to be used in infrared network attached video cameras in surveillance applications. The focal plane array consists of 352×288 uncooled microbolometer detectors with a pitch of 25 µm. The circuit features mismatch correction and a non-linear ramped current pulse scheme for biasing of the detectors, in order to relax the dynamic range requirement of preamplifiers and ADC imposed by detector process variation and self-heating during readout. The integrated circuit is designed in a 0.35 µm standard CMOS process and a smaller 32×32 size test chip has been fabricated for verification. The test chip shows RMS input referred noise of 17 µV at 60 frames/second and dissipates 170 mW of power.
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| 10. |
- ud Din, Imad, et al.
(författare)
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Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS
- 2012
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Ingår i: [Host publication title missing]. - 9781467322218
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Konferensbidrag (refereegranskat)abstract
- A differential LNA using capacitive shunt feedback is demonstrated in 65nm CMOS. The capacitive shunt feedback structure gives a wideband input matching, S11 <;-17 dB from 500MHz - 1 GHz for low band and S11 <;-20 dB from 1.1 GHz - 2.3GHz for high band. The NF for the complete receiver chain in low band and high band was measured to 3.3 dB and 3.9 dB, respectively. The 1-dB compression point with a 0dBm blocker present at 20MHz offset is 0dBm and the NFdsb with 0dBm blocker is 13 dB. In-band IIP3, and IIP2 are -14.8 dBm, and >;49 dBm, respectively for low band and -18.2dBm and >;44dBm for high band.
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