| 1. |
- Jafri, Syed. M. A. H., et al.
(författare)
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Energy-Aware Coarse-Grained Reconfigurable Architectures using Dynamically Reconfigurable Isolation Cells
- 2013
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Ingår i: Proceedings Of The Fourteenth International Symposium On Quality Electronic Design (ISQED 2013). - 9781467349529 ; , s. 104-111
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Konferensbidrag (refereegranskat)abstract
- This paper presents a self adaptive architecture to enhance the energy efficiency of coarse-grained reconfigurable architectures (CGRAs). Today, platforms host multiple applications, with arbitrary inter-application communication and concurrency patterns. Each application itself can have multiple versions (implementations with different degree of parallelism) and the optimal version can only be determined at runtime. For such scenarios, traditional worst case designs and compile time mapping decisions are neither optimal nor desirable. Existing solutions to this problem employ costly dedicated hardware to configure the operating point at runtime (using DVFS). As an alternative to dedicated hardware, we propose exploiting the reconfiguration features of modern CGRAs. Our solution relies on dynamically reconfigurable isolation cells (DRICs) and autonomous parallelism, voltage, and frequency selection algorithm (APVFS). The DRICs reduce the overheads of DVFS circuitry by configuring the existing resources as isolation cells. APVFS ensures high efficiency by dynamically selecting the parallelism, voltage and frequency trio, which consumes minimum power to meet the deadlines on available resources. Simulation results using representative applications (Matrix multiplication, FIR, and FFT) showed up to 23% and 51% reduction in power and energy, respectively, compared to traditional DVFS designs. Synthesis results have confirmed significant reduction in area overheads compared to state of the art DVFS methods.
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| 2. |
- SUBRAMANIYAN, KASYAB PARMESH, 1979, et al.
(författare)
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Manufacturable Nanometer Designs using Standard Cells with Regular Layout
- 2013
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Ingår i: Proceedings - International Symposium on Quality Electronic Design, ISQED. - 1948-3295 .- 1948-3287. - 9781467349529 ; , s. 398-405
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Konferensbidrag (refereegranskat)abstract
- In addition to performance considerations, designing VLSI circuits at nanometer-scale process technology nodes demands considerations related to manufacturability and cost. Regular layout patterns are known to enhance resilience to random as well as certain types of systematic variations. In this contribution we assess the implications of this layout regularity using design automation for Critical Feature Analysis (CFA) and raw metrics, such as via count. Using the ISCAS’89 benchmark suite, for each benchmark circuit we compare place-and-route implementations that are based on semi-regular and ultra-regular cell layouts. While the CFA counter-intuitively suggests that implementations using ultra-regular layouts have lower Design for Manufacturability (DFM) scores than those using semi-regular layouts, we find that ultra-regular layouts yield implementations with an average of 22% fewer vias at the cost of a small wire length increase.
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