| 1. |
- Ahmed Aamir, Syed, et al.
(författare)
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Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
- 2013
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE conference proceedings. - 9781467357609 ; , s. 381-384
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Konferensbidrag (refereegranskat)abstract
- This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.
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| 2. |
- Al-Obaidi, Mohammed, et al.
(författare)
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Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
- 2013
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Ingår i: 2013 IEEE International Symposium on Circuits and Systems (ISCAS). - 2158-1525 .- 0271-4310. - 9781467357623 - 9781467357609 ; , s. 293-296
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Konferensbidrag (refereegranskat)abstract
- In LTE base-stations, RoHC is a processingintensive algorithm that may limit the system from serving a large number of users when it is used to compress the VoIP packets of mobile traffic. In this paper, a hardware-software and a full-hardware solution are proposed to accelerate the RoHC compression algorithm in LTE base-stations and enhance the system throughput and capacity. Results for both solutions are discussed and compared with respect to design metrics like throughput, capacity, power consumption, and hardware resources. This comparison is instrumental in taking architectural level trade-off decisions in-order to meet the present day requirements and also be ready to support a future evolution. In terms of throughput, a gain of 20% (6250 packets/sec) is achieved in the HW-SW implementation by accelerating the Cyclic Redundancy Check (CRC) and the Least Significant Bit (LSB) encoding in hardware. The full-HW implementation leads to a throughput of 45 times (244000 packets/sec) compared to the SW-Only implementation. The full-HW solution consumes more Adaptive Look-Up Tables (7477 ALUTs) compared to the HW-SW solution (2614 ALUTs) when synthesized on Altera’s Arria II GX FPGA.
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| 3. |
- Boopal, Padma Prasad, et al.
(författare)
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A Reconfigurable FFT Architecture for Variable-Length and Multi-Streaming OFDM Standards
- 2013
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE. - 9781467357609 ; , s. 2066-2070
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Konferensbidrag (refereegranskat)abstract
- This paper presents a reconfigurable FFT architecture for variable-length and multi-streaming WiMax wireless standard. The architecture processes 1 stream of 2048-point FFT, up to 2 streams of 1024-point FFT or up to 4 streams of 512-point FFT. The architecture consists of a modified radix-2 single delay feedback (SDF) FFT. The sampling frequency of the system is varied in accordance with the FFT length. The latch-free clock gating technique is used to reduce power consumption. The proposed architecture has been synthesized for the Virtex-6 XCVLX760 FPGA. Experimental results show that the architecture achieves the throughput that is required by the WiMax standard and the design has additional features compared to the previous approaches. The design uses 1% of the total available FPGA resources and maximum clock frequency of 313.67 MHz is achieved. Furthermore, this architecture can be expanded to suit other wireless standards.
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| 4. |
- Farahini, Nasim, et al.
(författare)
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39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation
- 2013
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Ingår i: 2013 IEEE International Symposium on Circuits and Systems (ISCAS). - : IEEE. - 9781467357609 ; , s. 1448-1451
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Konferensbidrag (refereegranskat)abstract
- This paper presents an industrial case study of using a Coarse Grain Reconfigurable Architecture (CGRA) for a multi-mode accelerator for two kernels: FFT for the LTE standard and the Correlation Pool for the UMTS standard to be executed in a mutually exclusive manner. The CGRA multi-mode accelerator achieved computational efficiency of 39.94 GOPS/watt (OP is multiply-add) and silicon efficiency of 56.20 GOPS/mm2. By analyzing the code and inferring the unused features of the fully programmable solution, an in-house developed tool was used to automatically customize the design to run just the two kernels and the two efficiency metrics improved to 49.05 GOPS/watt and 107.57 GOPS/mm2. Corresponding numbers for the ASIC implementation are 63.84 GOPS/watt and 90.91 GOPS/mm2. Though the ASIC’s silicon and computational efficiency numbers are slightly better, the engineering efficiency of the pre-verified/characterized CGRA solution is at least 10X better than the ASIC solution.
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| 5. |
- Fazli Yeknami, Ali, et al.
(författare)
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A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices
- 2013
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Ingår i: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013. - 9781467357609 ; , s. 2010-2013
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Konferensbidrag (refereegranskat)abstract
- A 0.5-V ultra-low-power second-order DT DS modulator is presented in this paper for medical implant devices. The modulator employs 2nd-order passive low-pass filter and ultra-low-voltage building blocks, including preamplifier, regenerative comparator, and clock controller, in order to enable operation near 0.5 V supply. A low-noise and gain-enhanced single-stage preamplifier is developed using a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification scheme. Designed in a 65nm CMOS technology, the modulator achieves 65 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW from a 0.5 V supply. The modulator is functional at 0.45V and obtains 52 dB SNR, while consuming 200 nW.
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| 6. |
- Fazli Yeknami, Ali, et al.
(författare)
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A Variable Bandwidth Amplifier for a Dual-mode Low-Power ΔΣ Modulator in Cardiac Pacemaker System
- 2013
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Ingår i: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). - 9781467357609 ; , s. 1918-1921
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Konferensbidrag (refereegranskat)abstract
- This paper presents the design and implementation of a variable bandwidth amplifier intended for ultra-low-power biomedical implants in 65nm CMOS, providing tunable gain-bandwidth in three modes: 0.9 MHz, 1.7 MHz, and 2.3 MHz with consistent 56 dB DC gain. The amplifier consumes 180nW static power in the lowest bandwidth mode, and consumes 315 nW static power in the full bandwidth mode with an 8 pF load from a 0.9-V supply voltage. To illustrate the concept, the presented programmable bandwidth amplifier is applied in a dual-mode ΔΣ modulator aiming for sensing/measuring stage of a cardiac pacemaker.
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| 7. |
- Nidhi, U., et al.
(författare)
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High performance 3D-FFT implementation
- 2013
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Ingår i: Circuits and Systems (ISCAS), 2013 IEEE International Symposium on. - : IEEE. - 9781467357609 ; , s. 2227-2230
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Konferensbidrag (refereegranskat)abstract
- 3D FFT is a very data and compute intensive kernel encountered in many applications. We report a high performance design and implementation of 3D-FFT on a CGRA which supports partial reconfiguration. The hardware software multi clock design uses dynamic reconfiguration to reduce the required communication bandwidth to achieve a sustained throughput of 40 GOPS on a wordsize of 48 bits. Performance metrics including overheads and speed over software for implementations of up to 256 point 3D-FFT have been presented in the paper.
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| 8. |
- Ojani, Amin, et al.
(författare)
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A quadrature UWB frequency synthesizer with dynamic settling-time calibration
- 2013
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE. - 9781467357609 ; , s. 2480-2483
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Konferensbidrag (refereegranskat)abstract
- This paper presents a quadrature DLL-based architecture for WiMedia ultra-wideband (UWB) frequency synthesis. I and Q carriers are directly generated by combining the quadrature multi-phase outputs of the DLL, using separate edge combiners (EC). A variable-stage voltage-controlled delay line (VCDL) scheme is proposed to provide the corresponding output phases to each EC, without the need for multiplexing the DLL outputs for different bands. Moreover, to prevent possible synthesizer hopping time degradation due to dynamic variations in temperature and voltage, a monitoring mechanism is employed to measure the time error at the instant of band switching, and compensate for it if it is beyond a limited value. The Synthesizer is implemented in a standard 65-nm CMOS technology and the simulation results indicate a hopping time of 4.5 to 8.8 ns across process corners. Simulated phase noise at 1 MHz offset from 4488 MHz carrier is -115 dBc/Hz and the worst case spur suppression is -31 dBc. The synthesizer consumes 13.9 mA from a 1.2-V supply.
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| 9. |
- Pillai, Anu Kalidas, et al.
(författare)
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Low-complexity two-rate based multivariate impulse response reconstructor for time-skew error correction in m-channel time-interleaved ADCs
- 2013
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE. - 9781467357609 ; , s. 2936-2939
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Konferensbidrag (refereegranskat)abstract
- Nonuniform sampling occurs in time-interleaved analog-to-digital converters (TI-ADC) due to timing mismatches between the individual channel analog-to-digital converters (ADCs). Such nonuniformly sampled output will degrade the achievable resolution in a TI-ADC. To restore the degraded performance, digital time-varying reconstructors can be used at the output of the TI-ADC, which in principle, converts the nonuniformly sampled output sequence to a uniformly sampled output. As the bandwidth of these reconstructors increases, their complexity also increases rapidly. Also, since the timing errors change occasionally, it is important to have a reconstructor architecture that requires fewer coefficient updates when the value of the timing error changes. Multivariate polynomial impulse response reconstructor is an attractive option for an M-channel reconstructor. If the channel timing error varies within a certain limit, these reconstructors do not need any online redesign of their impulse response coefficients. This paper proposes a technique that can be applied to multivariate polynomial impulse response reconstructors in order to further reduce the number of fixed-coefficient multipliers, and thereby reduce the implementation complexity.
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| 10. |
- Ryman, Erik J, 1982, et al.
(författare)
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A SiGe 8-Channel Comparator for Application in a Synthetic Aperture Radiometer
- 2013
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Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - 0271-4310. - 9781467357609 ; , s. 845-848
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Konferensbidrag (refereegranskat)abstract
- We present a high-speed low-power 8-channel comparator tailored for the application of sampling antenna signals in a cross-correlator system for space-borne synthetic aperture radiometer instruments. Features like clock return path, per-channel offset calibration and bias current tuning make the comparator adaptable and gives the possibility to adjust the comparator for low power consumption, while keeping performance within the requirements of the cross-correlator system. The comparator has been implemented and fabricated in a 130-nm SiGe BiCMOS process. Measurements show that the comparator can perform sampling at a rate of 4.5 GS/s with a power consumption of 48 mW/channel or 1 GS/s with a power consumption of 17 mW/channel.
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