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- Espling, Daniel, et al.
(författare)
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Integration and evaluation of decentralized fairshare prioritization (Aequus)
- 2014
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Ingår i: Proceedings of the IEEE 28th International Parallel & Distributed Processing Symposium Workshops IPDPSW 2014. - : IEEE Computer Society. - 9781479941162 ; , s. 1198-1207
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Konferensbidrag (refereegranskat)abstract
- Fairshare is commonly one of the factors used by cluster resource management systems to prioritize jobs during scheduling. Despite the grid vision of a transparent and unified infrastructure, fairshare is normally calculated and enforced at the local cluster level rather than at a grid-wide scale. Aequus is a self-contained decentralized system for grid-wide fairshare job prioritization. Using Aequus, detailed global share policies can be combined with local cluster policies to offer a unified grid fairshare prioritization system where local administrations retain control over their clusters. This work shows how Aequus can be integrated with local resource management systems such as SLURM and Maui with minimal intrusion. Early results from production help assess the maturity of the system, and the system is further tested and evaluated for use at a nation-wide scale using workload modeling techniques. Statistical models are created based on historical national grid usage data, and synthetic traces based on these models are used to create a diverse input set used to exemplify system behavior. The system is shown to behave consistently despite great variations in job arrival patterns and partial participation of some of the collaborating installations.
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| 2. |
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| 3. |
- Netzer, Gilbert, 1978-, et al.
(författare)
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Exploiting DMA for Performance and Energy Optimized STREAM on a DSP
- 2014
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Ingår i: IPDPSW ’14. - 9781479941162 ; , s. 805-814
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Konferensbidrag (refereegranskat)abstract
- Energy efficiency is of major concern in HPC.DSP architectures have the potential to offer highly competitiveenergy efficiency for applications requiring 64-bit floatingpointprecision. For STREAM, we achieved 1.47GB/J energy efficiency and 96% DDR3 memory bandwidth utilization on the Texas Instruments TMS320C6678 DSP by using its DMAengines for prefetching to avoid cache misses, which cause pipeline stalls in the DSP’s cores, and to prevent write-allocate loads, which would significantly reduce performance. The DMA engines were also used to coordinate the DSPs cores and schedule main memory accesses to improve DDR3 bandwidth utilization. We briefly describe the instrumentation that we designed and implemented for accurate measurement of the core-related, on-chip memory, and DDR3 power consumption and the effectiveness of the DSP’s power saving mechanisms to trade-off performance and energy efficiency.
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