| 1. |
- Kim, Yooseong, et al.
(författare)
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WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores
- 2014
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Ingår i: Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS 2014). - : IEEE conference proceedings. - 9781479946914 ; , s. 179-188
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Konferensbidrag (refereegranskat)abstract
- Software Managed Multicore (SMM) architectures have advantageous scalability, power efficiency, and predictability characteristics, making SMM particularly promising for real-time systems. In SMM architectures, each core can only access its scratchpad memory (SPM); any access to main memory is done explicitly by DMA instructions. As a consequence, dynamic code management techniques are essential for loading program code from the main memory to SPM. Current state-of-the-art dynamic code management techniques for SMM architectures are, however, optimized for average-case execution time, not worst-case execution time (WCET), which is vital for hard real-time systems. In this paper, we present two novel WCET-aware dynamic SPM code management techniques for SMM architectures. The first technique is optimal and based on integer linear programming (ILP), whereas the second technique is a heuristic that is suboptimal, but scalable. Experimental results with benchmarks from Mälardalen WCET suite and MiBench suite show that our ILP solution can reduce the WCET estimates up to 80% compared to previous techniques. Furthermore, our heuristic can, for most benchmarks, find the same optimal mappings within one second on a 2GHz dual core machine.
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| 2. |
- Yip, Eugene, et al.
(författare)
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Relaxing the Synchronous Approach for Mixed-Criticality Systems
- 2014
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Ingår i: Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS). - : IEEE conference proceedings. - 9781479946914 ; , s. 89-100
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Konferensbidrag (refereegranskat)abstract
- Synchronous languages are widely used to design safety-critical embedded systems. These languages are based on the synchrony hypothesis, asserting that all tasks must complete instantaneously at each logical time step. This assertion is, however, unsuitable for the design of mixed-criticality systems, where some tasks can tolerate missed deadlines. This paper proposes a novel extension to the synchronous approach for supporting three levels of task criticality: life, mission, and non-critical. We achieve this by relaxing the synchrony hypothesis to allow tasks that can tolerate bounded or unbounded deadline misses. We address the issue of task communication between multi-rate, mixed-criticality tasks, and propose a deterministic lossless communication model. To maximize system utilization, we present a hybrid static and dynamic scheduling approach that executes schedulable tasks during slack time. Extensive benchmarking shows that our approach can schedule up to 15% more task sets and achieve an average of 5.38% better system utilization than the Early-Release EDF (ER-EDF) approach. Tasks are scheduled fairer under our approach and achieve consistently higher execution frequencies, but require more preemptions.
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| 3. |
- Zimmer, Michael, et al.
(författare)
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FlexPRET: A Processor Platform for Mixed-Criticality Systems
- 2014
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Ingår i: Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS). - : IEEE conference proceedings. - 9781479946914 ; , s. 101-110
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Konferensbidrag (refereegranskat)abstract
- Mixed-criticality systems, in which multiple tasks of varying criticality execute on a single hardware platform, are an emerging research area in real-time embedded systems. High-criticality tasks require spatial and temporal isolation guarantees for independent verification, and the task set should efficiently utilize hardware resources. Hardware-based isolation is desirable but often underutilizes hardware resources, which can consist of multiple single-core, multicore, or multithreaded processors. We present FlexPRET, a processor designed specifically for mixed-criticality systems by allowing each task to make a trade-off between hardware-based isolation and efficient processor utilization. FlexPRET uses fine-grained multithreading with flexible scheduling and timing instructions to provide this functionality.
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