| 1. |
- Alvbrant, Joakim, et al.
(författare)
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Transfer Characteristics and Bandwidth Limitation in a Linear-Drift Memristor Model
- 2015
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Ingår i: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD). - : IEEE. - 9781479998777 ; , s. 332-335
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Konferensbidrag (refereegranskat)abstract
- The linear-drift memristor model, suggested by HP Labs a few years ago, is used in this work together with two window functions. From the equations describing the memristor model, the transfer characteristics of a memristor is formulated and analyzed. A first-order estimation of the cut-off frequency is shown, that illustrates the bandwidth limitation of the memristor and how it varies with some of its physical parameters. The design space is elaborated upon and it is shown that the state speed, the variation of the doped and undoped regions of the memristor, is inversely proportional to the physical length, and depth of the device. The transfer characteristics is simulated for Joglekar-Wolf, and Biolek window functions and the results are analyzed. The Joglekar-Wolf window function causes a distinct behavior in the tranfer characteristics at cut-off frequency. The Biolek window function on the other hand gives a smooth state transfer function, at the cost of loosing the one-to-one mapping between charge and state. We also elaborate on the design constraints derived from the transfer characteristics.
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| 2. |
- Andersson, Niklas, et al.
(författare)
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Power-efficient time-to-digital converter for all-digital frequency locked loops
- 2015
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Ingår i: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479998777 ; , s. 300-303
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Konferensbidrag (refereegranskat)abstract
- An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This architecture allows for an area efficient and power efficient implementation. Thetarget application for the TDC is an all-digital frequency-locked loop which is alsooverviewed in the paper. A prototype chip has been implemented in a 65 nm CMOSprocess with an active core area of 75μmˆ120μm. The time resolution is 5.7 ps with apower consumption of 1.85 mW measured at 50 MHz sampling frequency.
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| 3. |
- Haque, Muhammad Fahim Ul, et al.
(författare)
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Combined RF and Multiphase PWM Transmitter
- 2015
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Ingår i: 2015 European Conference on Circuit Theory and Design (ECCTD). - : IEEE. - 9781479998777 ; , s. 264-267
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Konferensbidrag (refereegranskat)abstract
- This paper presents two novel transmitter architectures based on the combination of radio-frequency pulse-width modulation and multiphase pulse-width modulation. The proposed transmitter architectures provide good amplitude resolution and large dynamic range at high carrier frequency, which is problematic with existing radio-frequency pulse-width modulation based transmitters. They also have better power efficiency and smaller chip area compared to multiphase pulse-width modulation based transmitters.
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| 4. |
- Harikumar, Prakash, et al.
(författare)
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A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications
- 2016
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. - 9781479998777 ; 63:8, s. 743-747
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.
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| 5. |
- Harikumar, Prakash, et al.
(författare)
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A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications
- 2015
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Ingår i: 2015 European Conference on Circuit Theory and Design (ECCTD). - : IEEE. - 9781479998777 ; , s. 13-16
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Konferensbidrag (refereegranskat)abstract
- This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].
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| 6. |
- Ingemarsson, Carl, 1983-, et al.
(författare)
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On fixed-point implementation of symmetric matrix inversion
- 2015
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Ingår i: Proceedings of the European Conference on Circuit Theory and Design (ECCTD). - Piscataway, NJ, USA : IEEE. - 9781479998777 ; , s. 440-443
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Konferensbidrag (refereegranskat)abstract
- In this work we explore the trade-offs between established algorithms for symmetric matrix inversion for fixed-point hardware implementation. Inversion of symmetric positive definite matrices finds applications in many areas, e.g. in MIMO detection and adaptive filtering. We explore computational complexity and show simulation results where numerical properties are analyzed. We show that LDLT decomposition combined with equation system solving are the most promising algorithm for fixed-point hardware implementation. We further show that simply counting the number of operations does not establish a valid comparison between the algorithms as the required word lengths differ significantly.
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| 7. |
- Kazim, Muhammad Irfan, et al.
(författare)
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Complex path impedance estimation and matching requirements for body-coupled communication
- 2015
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Ingår i: Circuit Theory and Design (ECCTD), 2015 European Conference on. - : IEEE. - 9781479998777 ; , s. 424-427
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Konferensbidrag (refereegranskat)abstract
- Capacitive body coupled communication (BCC) channel has been modeled as a two-port complex path impedance matrix [Z] which varies as a function of ten different body positions over the frequency range of 1 MHz to 60 MHz. A systematic numerical simulation methodology has been used to estimate [Z] parameters. The estimated complex path impedance [Z] is a symmetric matrix showing BCC channel is a reciprocal network of passive components for given coupler configuration, body positions and frequency range. The estimated complex path impedance has been utilized to determine either input impedance Zin or output impedance Zout to conjugately match to Zs at transmitter or Zl at receiver, respectively for maximum power transfer. It has been found that the resistive matching below 1000 O and inductive matching between 0.5 ï¿œH to 5 ï¿œH on any side of the two ports can meet the conjugate matching requirements for maximum power transfer for the given body positions and frequency range.
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| 8. |
- Kazim, Muhammad Irfan, et al.
(författare)
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Realistic path loss estimation for capacitive body-coupled communication
- 2015
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Ingår i: Circuit Theory and Design (ECCTD), 2015 European Conference on. - : IEEE. - 9781479998777 ; , s. 173-176
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Konferensbidrag (refereegranskat)abstract
- Realistic estimation of path loss is vital for designing an effective capacitive body-coupled communication system. The estimation based on simplified analytical models, however, results in errors as they do not model capacitive couplers accurately and different body positions. The proposed efficient full-wave electromagnetic (EM) model takes into account the effect of capacitive coupler, electro-physiological properties of tissues in human body, different body positions and environment all together to realistically predict the path loss. A comparison of both approaches is made in this paper, showing the superior performance of the proposed model.
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| 9. |
- Nielsen Lönn, Martin, 1989-, et al.
(författare)
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Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems
- 2015
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Ingår i: 2015 European Conference on Circuit Theory and Design (ECCTD). - : IEEE. - 9781479998760 - 9781479998777 ; , s. 308-311
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Konferensbidrag (refereegranskat)abstract
- MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.
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| 10. |
- Ohlsson, Fredrik, et al.
(författare)
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Modelling squeeze film damping in packaged energy harvesters
- 2015
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Ingår i: 2015 European Conference on Circuit Theory and Design (ECCTD). - 9781479998777
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Konferensbidrag (refereegranskat)abstract
- We investigate the effects of fluidic damping on MEMS packaged energy harvesters using numerical simulations in COMSOL Multiphysics. In particular, we compare two models for including squeeze film damping in the case where the harvester is operating close to a wall; an equivalent mass damping based on approximate modal coefficients and the numerical solution of the Reynolds equation in the air gap between the wall and the structure. The models are evaluated on a bridge design harvester intended for automotive applications.
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