| 1. |
- Becker, Matthias, 1986-, et al.
(författare)
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Scheduling Multi-Rate Real-Time Applications on Clustered Many-Core Architectures with Memory Constraints
- 2018
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Ingår i: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). - 9781509006021 ; , s. 560-567
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Konferensbidrag (refereegranskat)abstract
- Access to shared memory is one of the main chal- lenges for many-core processors. One group of scheduling strategies for such platforms focuses on the division of tasks’ access to shared memory and code execution. This allows to orchestrate the access to shared local and off-chip memory in a way such that access contention between different compute cores is avoided by design. In this work, an execution framework is introduced that leverages local memory by statically allocating a subset of tasks to cores. This reduces the access times to shared memory, as off-chip memory access is avoided, and in turn improves the schedulability of such systems. A Constrained Programming (CP) formulation is presented to selects the statically allocated tasks and generates the complete system schedule. Evaluations show that the pro- posed approach yields an up to 21% higher schedulability ratio than related work, and a case study demonstrates its applicability to industrial problems.
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| 2. |
- Huang, Letian, et al.
(författare)
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A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip
- 2018
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Ingår i: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509006021 ; , s. 147-152
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Konferensbidrag (refereegranskat)abstract
- Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.
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| 3. |
- Jiang, Shuyan, et al.
(författare)
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Optimizing Dynamic Mapping Techniques for On-Line NoC Test
- 2018
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Ingår i: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). - : IEEE. - 9781509006021 ; , s. 227-232
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Konferensbidrag (refereegranskat)abstract
- With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the main goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring about the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle links are identified and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from when the application leaves the platform and a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping. This leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF, NN, CoNA, and WeNA.
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