| 1. |
- Galias, Zbigniew, et al.
(författare)
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On the Existence of the Double Scroll Attractor for the Chua's Circuit with a Smooth Nonlinearity
- 2018
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Ingår i: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). - : IEEE. - 9781538648810
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Konferensbidrag (refereegranskat)abstract
- In simulations of the Chua's circuit with a smooth nonlinearity for certain parameter values one observes the double scroll attractor. This attractor contains an unstable equilibrium, and typical trajectories belonging to the attractor may pass arbitrarily close to this equilibrium. In consequence, it is impossible to compute trajectories over the whole attractor using standard rigorous numerical integration procedures. This is due to the existence of trajectories which spend arbitrarily long time in a neighborhood of the equilibrium. In this work, a method to find enclosures of trajectories passing arbitrarily close to an unstable fixed point of spiral type is presented. This method is used to prove the existence of a trapping region enclosing the double scroll attractor for the Chua's circuit with a cubic nonlinearity.
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| 2. |
- Huan, Yuxiang, et al.
(författare)
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A 3D Tiled Low Power Accelerator for Convolutional Neural Network
- 2018
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Ingår i: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). - : IEEE. - 9781538648810
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Konferensbidrag (refereegranskat)abstract
- It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 x 14 x 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.
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| 3. |
- Jin, Yi, et al.
(författare)
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TMR Group Coding Method for Optimized SEU and MBU Tolerant Memory Design
- 2018
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Ingår i: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). - : IEEE. - 9781538648810
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Konferensbidrag (refereegranskat)abstract
- This work proposes a fault tolerant memory design using the method of Triple Module Redundancy (TMR) group coding to tolerant the Single-Event Upset (SEU) and Multi-Bit Upset (MBU) influence on memory devices in space environment. The group coding method uses different models to partition and code each word line in memory with Hamming code to achieve best performance. TMR group coding method further increases the capability of self-correction for the errors occurred in parity bits. The evaluation results show that the suggested approach can obtain improved correctness for the memory output with optimized tradeoff between reliability and cost. At 5% error rate, the probability of correct output reaches 70.78% with small cost increment. To achieve 90% reliability, the accuracy improvement is 31.9% compared to TMR with 9% increased area. This solution proposed is evaluated on the memory rich micro-coded processor, but can be further extended to other memory-based processors that need high reliability for the SEU and MBU influence in aerospace applications.
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