| 1. |
- Al-Khatib, Iyad, et al.
(författare)
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Performance Analysis and Design Space Exploration for High-End Biomedical Applications : Challenges and Solutions
- 2007
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Ingår i: Proceedings of the International Conference on Hardware - Software Codesign and System Synthesis. - New York, NY, USA : ACM. - 9781595938244 ; , s. 217-226
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Konferensbidrag (refereegranskat)abstract
- High-end biomedical applications are a good target for specific-purpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring andanalysis is an immediate example with a large potential market. Today, the lack of scalable hardware platforms limits real-time analysis capabilities of most portable ECG analyzers, and prevents the upgrade of analysis algorithms for better accuracy. Multiprocessor system-on-chip (MPSoC) technology, which is becoming main-stream in the domain of high-performance microprocessors, is becoming attractive even for power-constrained portable applications, due to the capability to provide scalable computation horsepower at an affordable power cost. This paper illustrates one of the first comprehensive HW/SW exploration frameworks to fully exploit MPSoC technology to improve the quality of real-time ECG analysis.
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| 2. |
- Pop, Paul, 1974-, et al.
(författare)
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Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems
- 2007
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Ingår i: 5th Intl. Conf. on Hardware/Software Codesign and System Synthesis CODES+ISSS,2007. - Salzburg, Austria : IEEE Computer Society Press. - 9781595938244 ; , s. 233-
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Konferensbidrag (refereegranskat)abstract
- In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Processes and messages are statically scheduled, and we use process re-execution for recovering from multiple transient faults. Addressing simultaneously energy and reliability is especially challenging because lowering the voltage to reduce the energy consumption has been shown to exponentially increase the number of transient faults. In addition, time-redundancy based fault-tolerance techniques such as re-execution and dynamic voltage scaling-based low-power techniques are competing for the slack in the schedules. Our approach decides the voltage levels and start times of processes and the transmission times of messages, such that the transient faults are tolerated, the timing constraints of the application are satisfied and the energy is minimized. We present a constraint logic programming- based approach which is able to find reliable and schedulable implementations within limited energy and hardware resources. The developed algorithms have been evaluated using extensive experiments.
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| 3. |
- Raudvere, Tarvo, et al.
(författare)
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Synchronization after design refinements with sensitive delay elements
- 2007
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Ingår i: Proceedings of the International Conference on HW/SW Codesign and System Synthesis. - New York, NY, USA : ACM. - 9781595938244
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Konferensbidrag (refereegranskat)abstract
- The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at a high level of abstraction. In synchronous models, a local refinement increasing the delay in a single computation block may affect the functionality of the entire model. We provide a synchronization algorithm that preserves the system's functionality after design refinements, by using additional synchronization delays and making some delays sensitive to their input values. The refined and synchronized model stays latency equivalent to the original model. The advantages of our approach are the following: (a) we remain fully within the synchronous model of computation, (b) we preserve the functionality of the existing computation blocks, and (c) we do not require additional computation resources, specific communication protocols, wrapper circuits around computation blocks or schedulers.
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