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- Nunez-Prieto, Ricardo, et al.
(författare)
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A Real-Time Gesture Recognition System with FPGA Accelerated ZynqNet Classification
- 2019
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Ingår i: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019 : NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. - 9781728127699 - 9781728127705
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Konferensbidrag (refereegranskat)abstract
- This paper presents a real-time hand gesture recognition system by accelerating a convolutional neural network (CNN) using FPGA platform. More specifically, ZynqNet is adopted and modified to fulfill the classification task of recognizing the Swedish manual alphabet, which is used by sign language users for spelling purposes, also known as fingerspelling. Data augmentation and transfer learning techniques have been used during the training phase to improve the classification accuracy up to 80.1%, even with an 8-bit ZynqNet model. Extensive analysis of memory requirements and data processing patterns has been performed to enable optimization techniques, including memory partitioning and register arrays. The resulting FPGA implementation on a Xilinx UltraScale device avoids the use of off-chip memories, which together with block-wise processing scheduling, achieves an image rate of 23.5 frames per second (FPS) at 200 MHz clock frequency.
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| 2. |
- Tan, Siyu, et al.
(författare)
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A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS
- 2019
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Ingår i: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019 : NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. - 9781728127705 - 9781728127699
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Konferensbidrag (refereegranskat)abstract
- This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.
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