| 1. |
- Fallah, M. K., et al.
(författare)
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Scalable parallel genetic algorithm for solving large integer linear programming models derived from behavioral synthesis
- 2020
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Ingår i: Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020. - : Institute of Electrical and Electronics Engineers Inc.. - 9781728165820 ; , s. 390-394
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Solving Integer Linear Programming (ILP) models generally lies in the category of NP-hard problems. Therefore, as the size of ILP models grows, the efficiency of exact algorithms for solving the models reduced significantly and for large models it is not possible to have the result. Genetic Algorithm (GA) is a metaheuristic method capable of adjusting and redesigning parameters and operations according to the characteristics of ILP models. Still GA has huge search space for large models and parallelization is a suitable technique to tackle this problem. This paper presents a scalable parallel GA to solve large ILP models derived from behavioral synthesis of digital circuits. We show that although models have non-binary variables, only binary variables are sufficient for coding chromosomes. We also use 'unknown' values for some genes to decrease the likelihood of inconsistency in the encoded constraints. Our experiments verify the efficiency and scalability of the proposed algorithm on multicore platforms. The proposed method outperforms IBM ILOG CPLEX 12.6 and MI-LXPM algorithm where the ILP models include 550 to 2258 int / binary decision variables. Also, the results indicate that the saturation point of using parallel processing elements for solving the large ILP models is at least 60.
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| 2. |
- Kessler, Christoph, et al.
(författare)
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Robustness and Energy-elasticity of Crown Schedules for Sets of Parallelizable Tasks on Many-core Systems with DVFS
- 2020
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Ingår i: 2020 28TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING (PDP 2020). - : IEEE COMPUTER SOC. - 9781728165820 ; , s. 136-143
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Konferensbidrag (refereegranskat)abstract
- Crown scheduling is a static scheduling approach for sets of parallelizable tasks with a common deadline, aiming to minimize energy consumption on parallel processors with frequency scaling. We demonstrate that crown schedules are robust, i. e. that the runtime prolongation of one task by a moderate percentage does not cause a deadline transgression by the same fraction. In addition, by speeding up some tasks scheduled after the prolonged task, the deadline can still be met at a moderate additional energy consumption. We present a heuristic to perform this re-scaling online. We evaluate our approach with scheduling experiments on synthetic task sets.
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| 3. |
- Litzinger, Sebastian, et al.
(författare)
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Maximizing Profit in Energy-Efficient Moldable Task Execution with Deadline
- 2020
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Ingår i: 2020 28TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING (PDP 2020). - : IEEE COMPUTER SOC. - 9781728165820 ; , s. 152-156
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Konferensbidrag (refereegranskat)abstract
- We consider static scheduling of parallelizable tasks onto machines with frequency scaling for the case that not all tasks can be executed prior to a deadline. We model this scenario from a HPC cluster operators perspective. We solve the combinatorial optimization problem to maximize the operators profit by integer linear programming and by a heuristic. We evaluate the heuristic with synthetic benchmark task sets and demonstrate that it achieves at most 20% less profit than the solution via linear programming, so that it can be used for large task sets where the latter is not feasible anymore.
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| 4. |
- Melot, Nicolas, et al.
(författare)
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Voltage Island-Aware Energy-Efficient Scheduling of Parallel Streaming Tasks on Many-Core CPUs
- 2020
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Ingår i: 2020 28TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING (PDP 2020). - : IEEE COMPUTER SOC. - 9781728165820 ; , s. 157-161
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Konferensbidrag (refereegranskat)abstract
- For multi- and many-core CPUs, dynamic voltage and frequency scaling (DVPS) for individual cores provides an effective way for energy-efficient execution of applications. However, this requires additional hardware within the chip that regulates voltage and frequency for each hardware sub-component that can be scaled separately. Because of the significant cost of this control hardware, it is often not realistic to provide such a regulator for each individual core. Instead, chip manufacturers group cores into islands consisting of multiple cores with a common regulator, and energy optimizing solutions must lake this constraint into account when assigning frequencies 10 jobs and cores. Crown Scheduling is a technique for the combined resource allocation, mapping and discrete DVFS-level selection for actor networks consisting of moldable parallel streaming tasks for energy efficient execution given a throughput constraint. We extend crown scheduling to compute correct schedules also in the presence of DVFS islands constraints. We find that, for most task sets, the crown scheduler computes almost equally good schedules for target architectures with and without island constraints.
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| 5. |
- Nazari, N., et al.
(författare)
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Multi-level Binarized LSTM in EEG Classification for Wearable Devices
- 2020
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Ingår i: Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020. - : Institute of Electrical and Electronics Engineers Inc.. - 9781728165820 ; , s. 175-181
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Konferensbidrag (refereegranskat)abstract
- Long Short-Term Memory (LSTM) is widely used in various sequential applications. Complex LSTMs could be hardly deployed on wearable and resourced-limited devices due to the huge amount of computations and memory requirements. Binary LSTMs are introduced to cope with this problem, however, they lead to significant accuracy loss in some applications such as EEG classification which is essential to be deployed in wearable devices. In this paper, we propose an efficient multi-level binarized LSTM which has significantly reduced computations whereas ensuring an accuracy pretty close to full precision LSTM. By deploying 5-level binarized weights and inputs, our method reduces area and delay of MAC operation about 31× and 27× in 65nm technology, respectively with less than 0.01% accuracy loss. In contrast to many compute-intensive deep-learning approaches, the proposed algorithm is lightweight, and therefore, brings performance efficiency with accurate LSTM-based EEG classification to realtime wearable devices.
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