| 1. |
- Arslan, Mehmet Ali, et al.
(författare)
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A comparative study of scheduling techniques for multimedia applications on SIMD pipelines
- 2015
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Ingår i: DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015). - 9783981537048 ; , s. 3-9
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Konferensbidrag (refereegranskat)abstract
- Parallel architectures are essential in order to take advantage of the parallelism inherent in streaming applications. One particular branch of these employ hardware SIMD pipelines. In this paper, we analyse several scheduling techniques, namely ad hoc overlapped execution, modulo scheduling and modulo scheduling with unrolling, all of which aim to efficiently utilize the special architecture design. Our investigation focuses on improving throughput while analysing other metrics that are important for streaming applications, such as register pressure, buffer sizes and code size. Through experiments conducted on several media benchmarks, we present and discuss trade-offs involved when selecting any one of these scheduling techniques.
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| 2. |
- Farserotu, J., et al.
(författare)
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Tactile prosthetics in WiseSkin
- 2015
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Ingår i: Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. - 9783981537048 ; 2015-April, s. 1695-1697
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Konferensbidrag (refereegranskat)abstract
- The use of prosthetic hands is limited in part by the lack of sensory feedback to the wearer. In order to provide sensory feedback, an adequate number of sensors must be integrated with the prosthesis. The WiseSkin project targets the use of artificial skin embedding ultra-low power wireless sensor nodes. This presentation provides an overview of the WiseSkin project and the current status of the developments.
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| 3. |
- Haghbayan, M. -H, et al.
(författare)
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Power-aware online testing of manycore systems in the dark silicon era
- 2015
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Ingår i: Proceedings -Design, Automation and Test in Europe, DATE. - : IEEE conference proceedings. - 9783981537048 ; , s. 435-440
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Konferensbidrag (refereegranskat)abstract
- Online defect screening techniques to detect runtime faults are becoming a necessity in current and near future technologies. At the same time, due to aggressive technology scaling into the nanometer regime, power consumption is becoming a significant burden. Most of today's chips employ advanced power management features to monitor the power consumption and apply dynamic power budgeting (i.e., capping) accordingly to prevent over-heating of the chip. Given the notable power dissipation of existing testing methods, one needs to efficiently manage the power budget to cover test process of a many-core system in runtime. In this paper, we propose a power-aware online testing method for many-core systems benefiting from advanced power management capabilities. The proposed power-aware method uses non-intrusive online test scheduling strategy to functionally test the cores in their idle period. In addition, we propose a test-aware utilization-oriented runtime mapping technique that considers the utilization of cores and their test criticality in the mapping process. Our extensive experimental results reveal that the proposed power-aware online testing approach can efficiently utilize temporarily free resources and available power budget for the testing purposes, within less than 1% penalty on system throughput for the 16nm technology.
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| 4. |
- Paone, E., et al.
(författare)
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Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints
- 2015
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Ingår i: Proceedings -Design, Automation and Test in Europe, DATE. - New Jersey : IEEE conference proceedings. - 9783981537048 ; , s. 736-741
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Konferensbidrag (refereegranskat)abstract
- When targeting an OpenCL application to platforms with multiple heterogeneous accelerators, task tuning and mapping have to cope with device-specific constraints. To address this problem, we present an innovative design flow for the customization and performance optimization of OpenCL applications on heterogeneous parallel platforms. It consists of two phases: 1) a tuning phase that optimizes each application kernel for a given platform and 2) a task-mapping phase that maximizes the overall application throughput by exploiting concurrency in the application task graph. The tuning phase is suitable for customizing parameterized OpenCL kernels considering device-specific constraints. Then, the mapping phase improves task-level parallelism for multi-device execution accounting for the overhead of memory transfers - overheads implied by multiple OpenCL contexts for different device vendors. Benefits of the proposed design flow have been assessed on a stereo-matching application targeting two commercial heterogeneous platforms.
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| 5. |
- Zhang, Ying, et al.
(författare)
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Temperature-Aware Software-Based Self-Testing for Delay Faults
- 2015
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Ingår i: <em>Proc. Design, Automation and Test in Europe Conference (DATE’15), Grenoble, France, Mar. 9-13, 2015.</em>. - 9783981537048
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Konferensbidrag (refereegranskat)abstract
- Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don’t address this problem properly. In this paper, a temperature-aware software-based selftesting (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates highquality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.
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