| 1. |
- Henkel, Christoph, et al.
(författare)
-
Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks
- 2012
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 74, s. 7-12
-
Tidskriftsartikel (refereegranskat)abstract
- The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3 x 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k LaxGeyOz, layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.
|
|
| 2. |
|
|
| 3. |
|
|
| 4. |
- Nagatsuma, H., et al.
(författare)
-
4H-SiC nMOSFETs with As-Doped S/D and NbNi silicide ohmic contacts
- 2016
-
Ingår i: 16th International Conference on Silicon Carbide and Related Materials, ICSCRM 2015. - : Trans Tech Publications Ltd. - 9783035710427 ; , s. 573-576
-
Konferensbidrag (refereegranskat)abstract
- 4H-SiC nMOSFETs with As-doped S/D and NbNi silicide ohmic contacts were demonstrated for radiation-hard CMOS electronics. The threshold voltage Vth was designed to be 3.0 V by TCAD simulation, and was 3.6 – 3.8 V at the fabricated devices. On / off ratio was approximately 105.
|
|
| 5. |
- Olsen, Sarah H., et al.
(författare)
-
Control of self-heating in thin virtual substrate strained Si MOSFETs
- 2006
-
Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9383 .- 1557-9646. ; 53:9, s. 2296-2305
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates,,the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good ON-state performance, OFF-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing high-performance strained Si devices suitable for a wide range of applications is thus presented.
|
|
| 6. |
- Varzgar, John B., et al.
(författare)
-
Reliability study of ultra-thin gate oxides on strained-Si/SiGe MOS structures
- 2006
-
Ingår i: Materials Science & Engineering. - : Elsevier BV. - 0921-5107 .- 1873-4944. ; 135:3, s. 203-206
-
Tidskriftsartikel (refereegranskat)abstract
- The reliability of gate oxides on bulk Si and strained Si (s-Si) has been evaluated using constant voltage stressing (CVS) to investigate their breakdown characteristics. The s-Si architectures exhibit a shorter life time compared to that of bulk Si, which is attributed to higher bulk oxide charges (Q(ox)) and increased surface roughness in the s-Si structures. The gate oxide in the s-Si structure exhibits a hard breakdown (HBD) at 1.9 x 10(4) s, whereas HBD is not observed in bulk Si up to a measurement period of 1.44 x 10(5) s. The shorter lifetime of the s-Si gate oxide is attributed to a larger injected charge (Q(inj)) compared to Q(inj) in bulk Si. Current-voltage (I-V) measurements for bulk Si samples at different stress intervals show an increase in stress induced leakage current (SILC) of two orders in the low voltage regime from zero stress time to up to 5 x 10(4) s. In contrast, superior performance enhancements in terms of drain current, maximum transconductance and effective channel mobility are observed in s-Si MOSFET devices compared to bulk Si. The results from this study indicate that further improvement in gate oxide reliability is needed to exploit the sustained performance enhancement of s-Si devices over bulk Si.
|
|
