| 1. |
- Abdul Waheed, Malik, 1981-, et al.
(författare)
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Generalized Architecture for a Real-time Computation of an Image Component Features on a FPGA
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- This paper describes a generalized architecture for real-time component labeling and computation of image component features. Computing real-time image component features is one of the most important paradigms for modern machine vision systems. Embedded machine vision systems demand robust performance, power efficiency as well as minimum area utilization. The presented architecture can easily be extended with additional modules for parallel computation of arbitrary image component features. Hardware modules for component labeling and feature calculation run in parallel. This modularization makes the architecture suitable for design automation. Our architecture is capable of processing 390 video frames per second of size 640x480 pixels. Dynamic power consumption is 24.20mW at 86 frames per second on a Xilinx Spartran6 FPGA.
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| 2. |
- Cheng, Xin, 1974-, et al.
(författare)
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Color Symbol Design and Its Classification for Optical Navigation
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- We explored the color symbol design and its recognition in image as reference structure for optical navigation. A colors pair was first determined as foreground and background from HSI color palette and then a color symbol was designed as reference structure. The advantage of using this selected color symbol is a significant reduction, up to 97%, of segmented image components as compared to the grey scale image used. The reduction of segmented components in image will result in saving the hardware resources e.g. memory and processing power which are very important constraint for embedded platforms. A color symbol pattern was designed, comprising of three concentric circles with selected color pair. Inside the inner most circle is the Area Of Interest (AOI), the contents of AOI depends on the particular application. A hardware centric image analysis algorithm is developed for easy and robust recognition. Image components are identified after preprocessing, segmentation and labeling. The color symbol can be recognized at a classification step. Evaluating a variety of viewing angles and reading distances ranging from 30 to 150 degrees and from 1 to 10 meters gives a classification success rate of 72 percent of the positions.
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| 3. |
- Cheng, Xin, 1974-, et al.
(författare)
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Optimized Color Pair Selection for Label Design
- 2011
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Ingår i: Proceedings Elmar - International Symposium Electronics in Marine. - Zadar, Croatia : IEEE conference proceedings. - 9789537044121 ; , s. 115-118
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Konferensbidrag (refereegranskat)abstract
- We present in this paper a technique for designing reference labels that can be used for optical navigation. We optimize the selection of foreground and background colors used for the printed reference labels. This optimization calibrates for individual color responses among printers and cameras such that the Signal to Noise Ratio (SNR) is maximized. Experiments show that we get slightly smaller SNR for the color labels compared to using a monochrome technique. However, the number of segmented image components is reduced significantly by as much as 78 percent. This reduction of number of image components will in turn reduce the memory storage requirement for the computing embedded system.
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| 4. |
- Malik, Abdul Waheed, 1981-, et al.
(författare)
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Comparison of Three Smart Camera Architectures for Real-time Machine Vision System
- 2013
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Ingår i: International Journal of Advanced Robotic Systems. - : SAGE Publications. - 1729-8806 .- 1729-8814. ; 10, s. Art. no. 402-
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a machine vision system for real-time computation of distance and angle of a camera from a set of reference points located on a target board. Three different smart camera architectures were explored to compare performance parameters such as power consumption, frame speed and latency. Architecture 1 consists of hardware machine vision modules modeled at Register Transfer (RT) level and a soft-core processor on a single FPGA chip. Architecture 2 is commercially available software based smart camera, Matrox Iris GT. Architecture 3 is a two-chip solution composed of hardware machine vision modules on FPGA and an external micro-controller. Results from a performance comparison show that Architecture 2 has higher latency and consumes much more power than Architecture 1 and 3. However, Architecture 2 benefits from an easy programming model. Smart camera system with FPGA and external microcontroller has lower latency and consumes less power as compared to single FPGA chip having hardware modules and soft-core processor.
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| 5. |
- Malik, Abdul Waheed, 1981-, et al.
(författare)
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Hardware Architecture for Real-time Computation of Image Component Feature Descriptors on a FPGA
- 2014
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Ingår i: International Journal of Distributed Sensor Networks. - : SAGE Publications. - 1550-1329 .- 1550-1477. ; , s. Art. no. 815378-
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Tidskriftsartikel (refereegranskat)abstract
- This paper describes a hardwarearchitecture for real-time image component labelingand the computation of image component featuredescriptors. These descriptors are object relatedproperties used to describe each image component.Embedded machine vision systems demand a robustperformance, power efficiency as well as minimumarea utilization, depending on the deployedapplication. In the proposed architecture, the hardwaremodules for component labeling and featurecalculation run in parallel. A CMOS image sensor(MT9V032), operating at a maximum clock frequencyof 27MHz, was used to capture the images. Thearchitecture was synthesized and implemented on aXilinx Spartan-6 FPGA. The developed architecture iscapable of processing 390 video frames per second ofsize 640x480 pixels. Dynamic power consumption is13mW at 86 frames per second.
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| 6. |
- Malik, Abdul Waheed, 1981-, et al.
(författare)
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Real-time Component Labelling with Centre of Gravity Calculation on FPGA
- 2011
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Ingår i: 2011 Proceedings of Sixth International Conference on Systems.
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a hardware unit for real time component labelling with Centre of Gravity (COG) calculation. The main targeted application area is light spots used as references for robotic navigation. COG calculation can be done in parallel with a single pass component labelling unit without first having to resolve merged labels. We present hardware architecture suitable for implementation of this COG unit on Field programmable Gate Arrays (FPGA). As result, we get high frame speed, low power and low latency. The device utilization and estimated power dissipation are reported for Xilinx Virtex II pro device simulated at 86 VGA sized frames per second. Maximum speed is 410 frames per second at 126 MHz clock.
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| 7. |
- Malik, Abdul Waheed, 1981-, et al.
(författare)
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Real Time Decoding of Color Symbol for Optical Positioning System
- 2015
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Ingår i: International Journal of Advanced Robotic Systems. - : SAGE Publications. - 1729-8806 .- 1729-8814. ; 12:5
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the design and real-time decoding of a color symbol that can be used as a reference marker for optical navigation. The designed symbol has a circular shape and is printed on paper using two distinct colors. This pair of colors is selected based on the highest achievable signal to noise ratio. The symbol is designed to carry eight bit information. Real time decoding of this symbol is performed using a heterogeneous combination of Field Programmable Gate Array (FPGA) and a microcontroller. An image sensor having a resolution of 1600 by 1200 pixels is used to capture images of symbols in complex backgrounds. Dynamic image segmentation, component labeling and feature extraction was performed on the FPGA. The region of interest was further computed from the extracted features. Feature data belonging to the symbol was sent from the FPGA to the microcontroller. Image processing tasks are partitioned between the FPGA and microcontroller based on data intensity. Experiments were performed to verify the rotational independence of the symbols. The maximum distance between camera and symbol allowing for correct detection and decoding was analyzed. Experiments were also performed to analyze the number of generated image components and sub-pixel precision versus different light sources and intensities. The proposed hardware architecture can process up to 55 frames per second for accurate detection and decoding of symbols at two Megapixels resolution. The power consumption of the complete system is 342mw.
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